From: Jose Abreu
Date: Tue, 14 Jan 2020 17:09:20 +0100
> Set of fixes for sefltests so that they work in Synopsys AXS101 board.
...
Applied patches 1-3, it looks like patch 4 went into another tree.
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From: Mike Rapoport
Date: Wed, 16 Jan 2019 15:44:15 +0200
> Add panic() calls if memblock_alloc*() returns NULL.
>
> Most of the changes are simply addition of
>
> if(!ptr)
> panic();
>
> statements after the calls to memblock_alloc*() variants.
>
> Exceptions are pcpu
From: Christoph Hellwig
Date: Mon, 10 Dec 2018 20:22:28 +0100
> On Mon, Dec 10, 2018 at 10:10:39AM -0800, David Miller wrote:
>> From: Christoph Hellwig
>> Date: Mon, 10 Dec 2018 17:32:56 +0100
>>
>> > Dave, can you pick the series up through the sparc tree? I co
From: Christoph Hellwig
Date: Mon, 10 Dec 2018 17:32:56 +0100
> Dave, can you pick the series up through the sparc tree? I could also
> merge it through the dma-mapping tree, but given that there is no
> dependency on it the sparc tree seem like the better fit.
I thought that some of this is a
From: Christoph Hellwig
Date: Sat, 8 Dec 2018 09:41:15 -0800
> There are enough common defintions that a single header seems nicer.
>
> Also drop the pointless include.
>
> Signed-off-by: Christoph Hellwig
> Acked-by: Sam Ravnborg
Acked-by: David S. Miller
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From: Christoph Hellwig
Date: Sat, 8 Dec 2018 09:41:13 -0800
> The only thing we need to explicitly pull in is the defines for the
> CPU type.
>
> Signed-off-by: Christoph Hellwig
Acked-by: David S. Miller
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From: Christoph Hellwig
Date: Sat, 8 Dec 2018 09:41:14 -0800
> It has nothing to do with the content of the pci.h header.
>
> Suggested by: Sam Ravnborg
> Signed-off-by: Christoph Hellwig
Acked-by: David S. Miller
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From: Christoph Hellwig
Date: Sat, 8 Dec 2018 09:36:59 -0800
> Move the alloc / free routines down the file so that we can easily use
> the map / unmap helpers to implement non-consistent allocations.
>
> Also drop the _coherent postfix to match the method name.
>
> Signed-off-by: Christoph He
From: Christoph Hellwig
Date: Sat, 8 Dec 2018 09:36:58 -0800
> Just allocate the memory and use map_page to map the memory.
>
> Signed-off-by: Christoph Hellwig
Acked-by: David S. Miller
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From: Christoph Hellwig
Date: Sat, 8 Dec 2018 09:37:00 -0800
> Just allocate the memory and use map_page to map the memory.
>
> Signed-off-by: Christoph Hellwig
Acked-by: David S. Miller
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From: Christoph Hellwig
Date: Sat, 8 Dec 2018 09:36:57 -0800
> Move the alloc / free routines down the file so that we can easily use
> the map / unmap helpers to implement non-consistent allocations.
>
> Also drop the _coherent postfix to match the method name.
>
> Signed-off-by: Christoph He
From: Christoph Hellwig
Date: Sat, 8 Dec 2018 09:41:12 -0800
> There is no good reason to have a double indirection for the sparc32
> dma ops, so remove the sparc32_dma_ops and define separate dma_map_ops
> instance for the different IOMMU types.
>
> Signed-off-by: Christoph Hellwig
Acked-by:
From: Christoph Hellwig
Date: Sat, 8 Dec 2018 09:41:10 -0800
> No need to BUG_ON() on the cache maintainance ops - they are no-ops
> by default, and there is nothing in the DMA API contract that prohibits
> calling them on sbus devices (even if such drivers are unlikely to
> ever appear).
>
> S
From: Christoph Hellwig
Date: Sat, 8 Dec 2018 09:41:11 -0800
> Factor the code to remap memory returned from the DMA coherent allocator
> into two helpers that can be shared by the IOMMU and direct mapping code.
>
> Signed-off-by: Christoph Hellwig
Acked-by: David S. Miller
From: Joel Fernandes
Date: Fri, 12 Oct 2018 05:50:46 -0700
> If its an issue, then how do transparent huge pages work on Sparc? I don't
> see the huge page code (move_huge_pages) during mremap doing anything special
> for Sparc architecture when moving PMDs..
This is because all huge pages are
From: "Kirill A. Shutemov"
Date: Fri, 12 Oct 2018 14:30:56 +0300
> I looked into the code more and noticed move_pte() helper called from
> move_ptes(). It changes PTE entry to suite new address.
>
> It is only defined in non-trivial way on Sparc. I don't know much about
> Sparc and it's hard for
From: Eugeniy Paltsev
Date: Thu, 26 Jul 2018 15:05:37 +0300
> As for today STMMAC_ALIGN macro (which is used to align DMA stuff)
> relies on L1 line length (L1_CACHE_BYTES).
> This isn't correct in case of system with several cache levels
> which might have L1 cache line length smaller than L2 li
From: Alexandru Gagniuc
Date: Fri, 28 Jul 2017 15:07:03 -0700
> Before the GMAC on the Anarion chip can be used, the PHY interface
> selection must be configured with the DWMAC block in reset.
>
> This layer covers a block containing only two registers. Although it
> is possible to model this as
From: Eugeniy Paltsev
Date: Tue, 18 Jul 2017 17:07:15 +0300
> Unconditional reset dwmac before HW init if reset controller is present.
>
> In existing implementation we reset dwmac only after second module
> probing:
> (module load -> unload -> load again [reset happens])
>
> Now we reset dwmac
From: Vlad Zakharov
Date: Wed, 29 Mar 2017 13:41:46 +0300
> After a new NAPI_STATE_MISSED state was added to NAPI we can get into
> this state and in such case we have to reschedule NAPI as some work is
> still pending and we have to process it. napi_complete_done() function
> returns false if we
From: Alexey Brodkin
Date: Mon, 6 Feb 2017 22:24:45 +0300
> Given there're default values mentioned in the PHY datasheet
> fall-back gracefully to them instead of silently return an error
> through the whole call-chain.
>
> This allows to use minimalistic description in DT if no special
> featu
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