y: Masahiro Yamada
Acked-by: Conor Dooley
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*surely* if no other arch needs to do that, then we are safe to also
not do it... Your logic seems right by me at least, especially given the
lack of flushes elsewhere.
Reviewed-by: Conor Dooley
Cheers,
Conor.
> Signed-off-by: Arnd Bergmann
> ---
> arch/riscv/mm/dma-noncoherent.c
n by the device.
>
> riscv also invalidates the caches before the transfer, which does
> not appear to serve any purpose.
Rationale makes sense to me..
Reviewed-by: Conor Dooley
Thanks for working on all of this Arnd!
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Hi Mike,
On Tue, Jan 31, 2023 at 08:41:49PM +0200, Mike Rapoport wrote:
> On Tue, Jan 31, 2023 at 05:47:24PM +0000, Conor Dooley wrote:
> > On Sun, Jan 29, 2023 at 02:42:35PM +0200, Mike Rapoport wrote:
> > > From: "Mike Rapoport (IBM)"
> > >
> >
Hey Mike,
On Sun, Jan 29, 2023 at 02:42:35PM +0200, Mike Rapoport wrote:
> From: "Mike Rapoport (IBM)"
>
> Every architecture that supports FLATMEM memory model defines its own
> version of pfn_valid() that essentially compares a pfn to max_mapnr.
>
> Use mips/powerpc version implemented as sta