as opposed to adding plat-anarion/--
because it doesn't add a bunch of extra files.
Signed-off-by: Alexandru Gagniuc
---
arch/arc/plat-sim/platform.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arc/plat-sim/platform.c b/arch/arc/plat-sim/platform.c
index 5cda56b..a5dbfab 100644
le binding with 'arc-'
Changes since v1:
* Updated CPU core clock to 24 MHz to match HW changes.
Alexandru Gagniuc (2):
ARC: [plat-sim] Add .compatible property for Adaptrum Anarion SOC
ARC: DTS: Add device-tree for Anarion-based development board
arch/arc/boot/dts/a
This is split into the SOC bindings, and the board dts. The Endor
board is currently an FPGA emulation. Once real, silicon arrives, we
plan to remove Endor support.
Signed-off-by: Alexandru Gagniuc
---
arch/arc/boot/dts/adaptrum_anarion.dtsi | 110
arch/arc/boot
On 08/13/2017 10:34 AM, Vineet Gupta wrote:
On 08/11/2017 10:55 PM, Alexandru Gagniuc wrote:
I was hoping to avoid the addition of extra source files for zero code
gain, though your proposal does work. However, since the platform
would be added unconditionally, would it make more sense to add
Hi Vineet,
On 08/10/2017 06:07 PM, Vineet Gupta wrote:
Hi Alexandru,
On 08/11/2017 12:58 AM, Alexandru Gagniuc wrote:
Hi,
Looking under arch/arc, I see the current way is to add a
plat-[socname] for each new SoC. However, it seems that plat-sim, and
plat-tb10x are just place-holders for the
Hi,
Looking under arch/arc, I see the current way is to add a plat-[socname]
for each new SoC. However, it seems that plat-sim, and plat-tb10x are
just place-holders for the compatible bindings.
I was going to do the same for plat-anarion, which required an early
boot workaround. However, wi
HY informs GMAC
about link state, GMAC immediately reports that upstream to ARC core
and here we are.
Now with that change we mask all individual IRQ lines making entire
system more fool-proof.
Signed-off-by: Alexey Brodkin
Cc: Eugeniy Paltsev
Cc: Alexandru Gagniuc
Tested-by: Alexand
robed and interrupt mapping established.
Signed-off-by: Alexandru Gagniuc
---
Changes since v1:
* None
arch/arc/Kconfig | 1 +
arch/arc/Makefile| 1 +
arch/arc/plat-anarion/Kconfig| 10 ++
arch/arc/plat-anarion/Makefile | 7 +++
arch/arc/plat-an
Signed-off-by: Alexandru Gagniuc
---
Changes since v1:
* Updated CPU core clock to 24 MHz to match HW changes.
arch/arc/boot/dts/adaptrum_anarion.dtsi | 108
arch/arc/boot/dts/adaptrum_anarion_fpga.dts | 49 +
2 files changed, 157 insertions
On 08/01/2017 11:23 PM, Vineet Gupta wrote:
On 08/02/2017 03:03 AM, Alex wrote:
On 07/25/2017 08:08 PM, Vineet Gupta wrote:
I have tried the workarouns I mentioned on top of linux 4.9.34, and it
works exactly as expected. however, on top of 4.13-rc3 [1], the story
is a lot different. As soon as
On 07/31/2017 03:43 PM, Marek Vasut wrote:
On 08/01/2017 12:20 AM, Alexandru Gagniuc wrote:
On 07/31/2017 02:33 PM, Marek Vasut wrote:
On 07/31/2017 07:17 PM, Alexandru Gagniuc wrote:
+struct anarion_qspi {
+structspi_nor nor;
+structdevice *dev;
+uintptr_t
On 07/31/2017 02:33 PM, Marek Vasut wrote:
On 07/31/2017 07:17 PM, Alexandru Gagniuc wrote:
Hi Marek,
Thank you again for your feedback. I've applied a majority of your
suggestions, and I am very happy with the result. I should have v2
posted within a day or so.
[snip]
+/*
+ * This
Hi Marek,
Me again!
On 07/29/2017 02:34 AM, Marek Vasut wrote:
On 07/29/2017 12:07 AM, Alexandru Gagniuc wrote:
+static void aspi_drain_fifo(struct anarion_qspi *aspi, uint8_t *buf, size_t
len)
+{
+ uint32_t data;
Is this stuff below something like ioread32_rep() ?
[snip
On 07/29/2017 02:34 AM, Marek Vasut wrote:
On 07/29/2017 12:07 AM, Alexandru Gagniuc wrote:
Add support for the QSPI controller found in Adaptrum Anarion SOCs.
This controller is designed specifically to handle SPI NOR chips, and
the driver is modeled as such.
Because the system is emulated on
robed and interrupt mapping established.
Signed-off-by: Alexandru Gagniuc
---
arch/arc/Kconfig | 1 +
arch/arc/Makefile| 1 +
arch/arc/plat-anarion/Kconfig| 10 ++
arch/arc/plat-anarion/Makefile | 7 +++
arch/arc/plat-anarion/platform.c
Signed-off-by: Alexandru Gagniuc
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
b/Documentation/devicetree/bindings/vendor-prefixes.txt
index daf465be..33ee112 100644
--- a
Signed-off-by: Alexandru Gagniuc
---
arch/arc/boot/dts/adaptrum_anarion.dtsi | 107
arch/arc/boot/dts/adaptrum_anarion_fpga.dts | 49 +
2 files changed, 156 insertions(+)
create mode 100644 arch/arc/boot/dts/adaptrum_anarion.dtsi
create mode 100644
s are implemented at
this time.
Signed-off-by: Alexandru Gagniuc
---
.../devicetree/bindings/mtd/anarion-quadspi.txt| 22 +
drivers/mtd/spi-nor/Kconfig| 7 +
drivers/mtd/spi-nor/Makefile | 1 +
drivers/mtd/spi-nor/anarion-quad
o
get any meaningful speed measurements with the CPU clock at 12 MHz.
Once the silicon arrives, I'll look at the performance aspect and
other aspects that we simply can't support on an FPGA.
Alex
Alexandru Gagniuc (5):
of: Add vendor prefix for Adaptrum, Inc.
ARC: [plat-anarion]
it's much more intuitive to include this in the
glue layer instead.
At this time only RGMII is supported, because it is the only mode
which has been validated hardware-wise.
Signed-off-by: Alexandru Gagniuc
---
.../devicetree/bindings/net/anarion-gmac.txt | 25
drivers/net/e
Hi,
I'm getting a storm of these messages when trying to boot an in-house
ASIC with an ARC770. This only happens with an ethernet cable plugged
in. I've learned that the actual interrupt number is 21. The issue is
that the irq_find_mapping() in __handle_domain_irq() fails to find a
mapping fo
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