[PATCH v4 2/2] mm: use clear_user_(high)page() for arch with special user folio handling

Some architectures have special handling after clearing user folios: architectures, which set cpu_dcache_is_aliasing() to true, require flushing dcache; arc, which sets cpu_icache_is_aliasing() to true, changes folio->flags to make icache coherent to dcache. So __GFP_ZERO using only clear_page() is

[PATCH v4 1/2] Introduce cpu_icache_is_aliasing() across all architectures

In commit eacd0e950dc2 ("ARC: [mm] Lazy D-cache flush (non aliasing VIPT)"), arc adds the need to flush dcache to make icache see the code page change. This also requires special handling for clear_user_(high)page(). Introduce cpu_icache_is_aliasing() to make MM code query special clear_user_(high)

Re: [PATCH v3 1/2] Introduce cpu_icache_is_aliasing() across all architectures

On 2024-12-07 12:01, Mathieu Desnoyers wrote: On 2024-12-07 11:55, Zi Yan wrote: In commit eacd0e950dc2 ("ARC: [mm] Lazy D-cache flush (non aliasing VIPT)"), arc adds the need to flush dcache to make icache see the code page change. This also requires special handling for clear_user_(high)page()

Re: [PATCH v3 2/2] mm: use clear_user_(high)page() for arch with special user folio handling

On 2024-12-07 11:55, Zi Yan wrote: For architectures setting cpu_dcache_is_aliasing() to true, which require flushing dcache, and arc setting cpu_icache_is_aliasing() to true changes folio->flags to make icache coherent to dcache after clearing a user folio, __GFP_ZERO using only clear_page() is

Re: [PATCH v3 1/2] Introduce cpu_icache_is_aliasing() across all architectures

On 2024-12-07 11:55, Zi Yan wrote: In commit eacd0e950dc2 ("ARC: [mm] Lazy D-cache flush (non aliasing VIPT)"), arc adds the need to flush dcache to make icache see the code page change. This also requires special handling for clear_user_(high)page(). Introduce cpu_icache_is_aliasing() to make MM

[PATCH v3 2/2] mm: use clear_user_(high)page() for arch with special user folio handling

For architectures setting cpu_dcache_is_aliasing() to true, which require flushing dcache, and arc setting cpu_icache_is_aliasing() to true changes folio->flags to make icache coherent to dcache after clearing a user folio, __GFP_ZERO using only clear_page() is not enough to zero user folios and cl

[PATCH v3 1/2] Introduce cpu_icache_is_aliasing() across all architectures

In commit eacd0e950dc2 ("ARC: [mm] Lazy D-cache flush (non aliasing VIPT)"), arc adds the need to flush dcache to make icache see the code page change. This also requires special handling for clear_user_(high)page(). Introduce cpu_icache_is_aliasing() to make MM code query special clear_user_(high)