Re: [PATCH 08/21] riscv: dma-mapping: only invalidate after DMA, not flush

On 27 Mar 2023, at 13:13, Arnd Bergmann wrote: > > From: Arnd Bergmann > > No other architecture intentionally writes back dirty cache lines into > a buffer that a device has just finished writing into. If the cache is > clean, this has no effect at all, but if a cacheline in the buffer has > a

Re: [PATCH 08/21] riscv: dma-mapping: only invalidate after DMA, not flush

On Mon, Mar 27, 2023 at 02:13:04PM +0200, Arnd Bergmann wrote: > From: Arnd Bergmann > > No other architecture intentionally writes back dirty cache lines into > a buffer that a device has just finished writing into. If the cache is > clean, this has no effect at all, but > if a cacheline in the

Re: [PATCH 09/21] riscv: dma-mapping: skip invalidation before bidirectional DMA

On Mon, Mar 27, 2023 at 02:13:05PM +0200, Arnd Bergmann wrote: > From: Arnd Bergmann > > For a DMA_BIDIRECTIONAL transfer, the caches have to be cleaned > first to let the device see data written by the CPU, and invalidated > after the transfer to let the CPU see data written by the device. > >