I see a discrepancy here ...
arch/arc/include/asm/shmparam.h:
/* Handle upto 2 cache bins */
#define SHMLBA (2 * PAGE_SIZE)
arch/arc/include/asm/cacheflush.h:
#define CACHE_COLORS_NUM4
(there are some other problems with the arc cache flushing code; I'm
working on patches to address th
From: Pavel Kozlov
Add support for the configuration with 4K Page Size and enabled ARC_PAE40.
Set two-level Page Table to 10:9:12, as with PAE40 a 4k page can settle
only 512 entries (with PAE40 size of PTE entry increases from 4 to 8
bytes).
In this configuration the Page Table can describe onl
On 10/02/2023 10:17, Shahab Vahedi wrote:
On 2/9/23 21:27, Arnout Vandecappelle wrote:
On 09/02/2023 13:23, Shahab Vahedi wrote:
On 2/8/23 17:36, Arnout Vandecappelle wrote:
It's not clear to me why you did a revert of the cookie feature rather than
using those patches. I think the first
On 2/9/23 21:27, Arnout Vandecappelle wrote:
>
> On 09/02/2023 13:23, Shahab Vahedi wrote:
>>
>> On 2/8/23 17:36, Arnout Vandecappelle wrote:
>>>
>>> It's not clear to me why you did a revert of the cookie feature rather than
>>> using those patches. I think the first two or three should be suffic
