On Thu, Aug 12, 2021 at 04:37:50PM -0700, Vineet Gupta wrote:
> ARCv2 MMU is software walked and Linux implements 2 levels of paging: pgd/pte.
> Forthcoming hw will have multiple levels, so this change preps mm code
> for same. It is also fun to try multi levels even on soft-walked code to
> ensure
Heh,
"Don't pollute mmu.h and cache.h with some of ARC internal bootlog/setup
related functions.
move them aside to setup.h"
is still not there :)
On Thu, Aug 12, 2021 at 04:37:37PM -0700, Vineet Gupta wrote:
> Signed-off-by: Vineet Gupta
> ---
> arch/arc/include/asm/cache.h | 4
> arch
On Thu, Aug 12, 2021 at 04:37:35PM -0700, Vineet Gupta wrote:
> MMU SCRATCH_DATA0 register is intended to cache task pgd. However in
> ARC700 SMP port, it has to be repurposed for reentrant interrupt
> handling, while UP port doesn't. We currently ahandle boe usecases
On Thu, Aug 12, 2021 at 04:37:34PM -0700, Vineet Gupta wrote:
> Hi,
>
> Big pile of ARC mm changes to prepare for 3 or 4 levels of paging (from
> current 2) needed for new hardware page walked MMUv6 (in aRCv3 ISA based
> cores).
>
> Most of these changes are incremental cleanups to make way for 1
