Ok, enter and leave will officially get to be TCG code.
To be honest initially we thought that helper code would be preferable
to TCG one. Apparently we were wrong. :-)
Thanks for your quick feedback.
On 1/15/21 9:53 PM, Richard Henderson wrote:
> On 1/15/21 11:48 AM, Cupertino Miranda wrote:
>>
On 1/15/21 11:48 AM, Cupertino Miranda wrote:
>> In the case of enter or leave, this is one load/store plus one addition,
>> followed by a branch. All of which is encoded as fields in the instruction.
>> Extremely simple.
>
> So your recommendation is leave the conditional exception triggering of
On 1/15/21 11:28 AM, Shahab Vahedi wrote:
>>> +cpu_stl_data(env, tmp_sp, CPU_FP(env));
>>> +}
>>
>> And what if these stores raise an exception? I doubt you're going to get an
>> exception at the correct pc.
>
> I've added a few bad-weather test cases [1] and they work as expected. In
On 1/15/21 8:31 PM, Richard Henderson wrote:
> On 1/15/21 7:11 AM, Cupertino Miranda wrote:
>>> Similarly. I think that both of these could be implemented entirely in
>>> translate, which is what
>>>
+bool restore_fp= u7 & 0x10; /* u[4] indicates if fp must be saved
*/
Thanks for your quick reply.
On 1/15/21 8:17 PM, Richard Henderson wrote:
> On 1/15/21 7:11 AM, Cupertino Miranda wrote:
>>> On 11/11/20 10:17 AM, cupertinomira...@gmail.com wrote:
+/*
+ * The macro to add boiler plate code for conditional execution.
+ * It will add tcg_gen codes on
Hi Richard,
On 12/1/20 10:35 PM, Richard Henderson wrote:
> On 11/11/20 10:17 AM, cupertinomira...@gmail.com wrote:
>> From: Cupertino Miranda
>> +void helper_enter(CPUARCState *env, uint32_t u6)
>> +{
>> +/* nothing to do? then bye-bye! */
>> +if (!u6) {
>> +return;
>> +}
>>
On 1/15/21 7:11 AM, Cupertino Miranda wrote:
>> Similarly. I think that both of these could be implemented entirely in
>> translate, which is what
>>
>>> +bool restore_fp= u7 & 0x10; /* u[4] indicates if fp must be saved
>>> */
>>> +bool restore_blink = u7 & 0x20; /* u[5] indicates s
On 1/15/21 7:11 AM, Cupertino Miranda wrote:
>> On 11/11/20 10:17 AM, cupertinomira...@gmail.com wrote:
>>> +/*
>>> + * The macro to add boiler plate code for conditional execution.
>>> + * It will add tcg_gen codes only if there is a condition to
>>> + * be checked (ctx->insn.cc != 0). This macro
- Enable C++ support
- Don't strip executables
- Add minimal debug symbols
- Enable strace and openssh
- Enable perf (and elfutils)
Signed-off-by: Vineet Gupta
---
configs/snps_archs38_hsdk_defconfig | 11 +++
1 file changed, 11 insertions(+)
diff --git a/configs/snps_archs38_hsdk_
For the HS48 processor, BR currently builds with -mcpu=hs4x_rel31 which
generates suboptimal code as it inhibits delay slot and back-back ST and so on.
Enable a new variant to build with -mcpu=hs4x for normal codegen.
Signed-off-by: Vineet Gupta
---
arch/Config.in.arc | 16 +++-
1 f
Hi,
PFA assorted ARC changes. Main being a hw config for -mcpu=hs4x which
schedules code for HS48x dual issue pipeline.
Thx,
-Vineet
Vineet Gupta (4):
ARC: Add support for generic HS48 processor
configs/snps_archs38_hsdk_defconfig: refresh defconfig
configs/snps_archs38_hsdk_defconfig: swi
We are no longer actively working on uClibc and hard-float support is
pretty stable, so make that default for HSDK boards
The hard-float setting is a bit convulated since current ARC gcc lacks
--with-fpu - so this is done with BR2_TARGET_OPTIMIZATION
Signed-off-by: Vineet Gupta
---
configs/snps
No config changes done
| make snps_archs38_hsdk_defconfig
| make savedefconfig
Signed-off-by: Vineet Gupta
---
configs/snps_archs38_hsdk_defconfig | 22 +-
1 file changed, 5 insertions(+), 17 deletions(-)
diff --git a/configs/snps_archs38_hsdk_defconfig
b/configs/snps_arch
On 1/15/21 7:11 AM, Cupertino Miranda wrote:
> As you know, we reused the code from binutils to implement the decoder.
> In that sense, we kindly request to allow us to do it through binutils
> development flow later on. We will change the tables in binutils
> and those changes will also be mirror
>> +
>> +assert(ctx->insn.limm_p == 0 && !in_delay_slot);
>> +
>> +if (ctx->insn.limm_p == 0 && !in_delay_slot) {
>> +in_delay_slot = true;
>> +uint32_t cpc = ctx->cpc;
>> +uint32_t pcl = ctx->pcl;
>> +insn_t insn = ctx->insn;
>> +
>> +ctx->cpc = ctx-
> On 11/11/20 10:17 AM, cupertinomira...@gmail.com wrote:
>> +/*
>> + * The macro to add boiler plate code for conditional execution.
>> + * It will add tcg_gen codes only if there is a condition to
>> + * be checked (ctx->insn.cc != 0). This macro assumes that there
>> + * is a "ctx" variable of t
>> +void QEMU_NORETURN helper_halt(CPUARCState *env, uint32_t npc)
>> +{
>> +CPUState *cs = env_cpu(env);
>> +if (env->stat.Uf) {
>> +cs->exception_index = EXCP_PRIVILEGEV;
>> +env->causecode = 0;
>> +env->param = 0;
>> + /* Restore PC such that we point at t
Hi Richard,
Sorry to take so long to get through the changes after your review.
I am still going through the improving process and waiting for some
internal company approval to publish the generator of the TCG
instruction definitions, as we have discussed.
Nevertheless, there are some questions
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