On 5/4/20 2:21 PM, Vineet Gupta wrote:
> On 4/22/20 6:41 PM, Vineet Gupta wrote:
>> Hi,
>>
>> This patchset implements glibc port to ARC HS48x processor from Synopsys.
>
> ping !
ping ^2
I have rebased and adjusted the v6 patch for semaphore header unification. Would
appreciate more technincal r
From: Mike Rapoport
All architectures tables define pgd_offset() as an entry in the array of
PGDs indexed by the pgd_index(), where pgd_index() is
(address >> PGD_SHIFT) & (PTRS_PER_PGD - 1)
For the most cases, the pgd_offset() uses mm->pgd as the pointer to the
top-level page directory
From: Mike Rapoport
All architectures define pmd_index() as
(address >> PMD_SHIFT) & (PTRS_PER_PMD - 1)
and all architectures that have at least three-level page tables define
pmd_offset() as an entry in the array of PMDs indexed by the pmd_index().
For the most architectures the pmd_o
From: Mike Rapoport
All architectures that have at least four-level page tables define
pud_offset() as an entry in the array of PUDs indexed by the pud_index(),
where pud_index() is
(address >> PUD_SHIFT) & (PTRS_PER_PUD - 1)
For the most architectures the pud_offset() implementation re
From: Mike Rapoport
The powerpc 32-bit implementation of pgtable has nice shortcuts for
accessing kernel PMD and PTE for a given virtual address.
Make this helpers available for all architectures.
Signed-off-by: Mike Rapoport
---
arch/arc/mm/highmem.c | 10 +---
arch/arm/ma
From: Mike Rapoport
All architectures define pte_index() as
(address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)
and all architectures define pte_offset_kernel() as an entry
in the array of PTEs indexed by the pte_index().
For the most architectures the pte_offset_kernel() implementation relie
From: Mike Rapoport
There are three cases for the trampoline initialization:
* 32-bit does nothing
* 64-bit with kaslr disabled simply copies a PGD entry from the direct map
to the trampoline PGD
* 64-bit with kaslr enabled maps the real mode trampoline at PUD level
These cases are currently d
From: Mike Rapoport
The comment about page table allocation functions resides in
include/asm/motorola_pgtable.h while the functions live in
include/asm/motorola_pgaloc.h.
Move the comment close to the code.
Signed-off-by: Mike Rapoport
---
arch/m68k/include/asm/motorola_pgalloc.h | 6 ++
From: Mike Rapoport
The cache_page() and nocache_page() functions are only used by the motorola
MMU variant for setting caching attributes for the page table pages.
Move the definitions of these functions from
arch/m68k/include/asm/motorola_pgtable.h closer to their usage in
arch/m68k/mm/motorol
From: Mike Rapoport
All architectures use pXd_index() to get an entry in the page table page
corresponding to a virtual address.
Align csky with other architectures.
Signed-off-by: Mike Rapoport
---
arch/csky/include/asm/pgtable.h | 5 ++---
arch/csky/mm/fault.c| 2 +-
arch/csky/m
From: Mike Rapoport
The replacement of with made the include
of the latter in the middle of asm includes. Fix this up with the aid of
the below script and manual adjustments here and there.
import sys
import re
if len(sys.argv) is not 3:
print "USAGE: %s "
From: Mike Rapoport
The linux/mm.h header includes to allow inlining of the
functions involving page table manipulations, e.g. pte_alloc() and
pmd_alloc(). So, there is no point to explicitly include in
the files that include .
The include statements in such cases are remove with a simple loop
From: Mike Rapoport
Hi,
The low level page table accessors (pXY_index(), pXY_offset()) are
duplicated across all architectures and sometimes more than once. For
instance, we have 31 definition of pgd_offset() for 25 supported
architectures.
Most of these definitions are actually identical and t
Hi Claudiu,
ping!
Is is possible to switch between mcount modes (Linux-style <-> baremetal-style)
via command-line options for ARC GCC?
>From: Alexey Brodkin
>Sent: Thursday, April 2, 2020 17:15
>To: Claudiu Zissulescu Ianculescu
>Cc: linux-ker...@vger.kernel.org; Steven Rostedt; Ingo Molnar;
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