On 5/30/19 11:55 AM, Paul E. McKenney wrote:
>
>> I'm not sure how to interpret "natural alignment" for the case of double
>> load/stores on 32-bit systems where the hardware and ABI allow for 4 byte
>> alignment (ARCv2 LDD/STD, ARM LDRD/STRD )
>>
>> I presume (and the question) that lkmm doesn
On Thu, May 30, 2019 at 11:22:42AM -0700, Vineet Gupta wrote:
> Hi Peter,
>
> Had an interesting lunch time discussion with our hardware architects
> pertinent to
> "minimal guarantees expected of a CPU" section of memory-barriers.txt
>
>
> | (*) These guarantees apply only to properly aligned
Hi Peter,
Had an interesting lunch time discussion with our hardware architects pertinent
to
"minimal guarantees expected of a CPU" section of memory-barriers.txt
| (*) These guarantees apply only to properly aligned and sized scalar
| variables. "Properly sized" currently means variables
On 5/17/19 3:23 PM, Eugeniy Paltsev wrote:
> Hmmm,
>
> so load the bool variable from memory is converted to such asm code:
>
> ->8---
> ldb r2,[some_bool_address]
> extb_sr2,r2
> ->8---
>
> Could you please describe that
On 5/14/19 5:29 PM, Vineet Gupta wrote:
> In case of successful page fault handling, this patch releases mmap_sem
> before updating the perf stat event for major/minor faults. So even
> though the contention reduction is NOT supe rhigh, it is still an
> improvement.
This patch causes regression: L
