[PATCH 4/4 v2] arc: fix printk warning in arc/plat-eznps/mtm.c

2018-07-26 Thread rd_dunlab
From: Randy Dunlap Fix printk format warning in arch/arc/plat-eznps/mtm.c: In file included from ../include/linux/printk.h:7, from ../include/linux/kernel.h:14, from ../include/linux/list.h:9, from ../include/linux/smp.h:12, fro

[PATCH 2/4 v2] arc: fix type warnings in arc/mm/cache.c

2018-07-26 Thread rd_dunlab
From: Randy Dunlap Fix type warnings in arch/arc/mm/cache.c. ../arch/arc/mm/cache.c: In function 'flush_anon_page': ../arch/arc/mm/cache.c:1062:55: warning: passing argument 2 of '__flush_dcache_page' makes integer from pointer without a cast [-Wint-conversion] __flush_dcache_page((phys_addr

[PATCH 3/4 v2] arc: fix data type errors in platform headers

2018-07-26 Thread rd_dunlab
From: Randy Dunlap Add to fix build errors. Both ctop.h and use u32 types and cause many errors. Examples: ../include/soc/nps/common.h:71:4: error: unknown type name 'u32' u32 __reserved:20, cluster:4, core:4, thread:4; ../include/soc/nps/common.h:76:3: error: unknown type name 'u32' u3

[PATCH 0/4 v2] arc: some allmodconfig build fixes

2018-07-26 Thread rd_dunlab
From: Randy Dunlap Hi, Here are a few patches that fix build errors or warnings that I encountered while doing arc "allmodconfig" builds. These patches do not fix all of the build issues. arch/arc/include/asm/delay.h|3 +++ arch/arc/mm/cache.c |7 -

[PATCH 1/4 v2] arc: fix build errors in arc/include/asm/delay.h

2018-07-26 Thread rd_dunlab
From: Randy Dunlap Fix build errors in arch/arc/'s delay.h: - add "extern unsigned long loops_per_jiffy;" - add for "u64" In file included from ../drivers/infiniband/hw/cxgb3/cxio_hal.c:32: ../arch/arc/include/asm/delay.h: In function '__udelay': ../arch/arc/include/asm/delay.h:61:12: error: 'u

Re: [PATCH] ARC: fix broken noncoherent cache ops

2018-07-26 Thread Vineet Gupta
On 07/26/2018 02:08 AM, Christoph Hellwig wrote: > On Tue, Jul 24, 2018 at 05:13:02PM +0300, Eugeniy Paltsev wrote: >> All DMA devices on ARC haven't worked with SW cache control >> since commit a8eb92d02dd7 ("arc: fix arc_dma_{map,unmap}_page") >> This happens because we don't check direction argu

Re: [PATCH v2 2/2] ARC: add SMP_CACHE_BYTES value validate

2018-07-26 Thread Vineet Gupta
On 07/26/2018 06:15 AM, Eugeniy Paltsev wrote: > Check that SMP_CACHE_BYTES (and hence ARCH_DMA_MINALIGN) is larger > or equal to any cache line length by comparing it with values > previously read from ARC cache BCR registers. > > Signed-off-by: Eugeniy Paltsev > --- > Changes v1->v2: > * None.

Re: [PATCH] Fix the ld flags not be applied to tst-execstack-mod.so

2018-07-26 Thread Joseph Myers
On Thu, 26 Jul 2018, Zong Li wrote: > In glibc now, this option doesn't pass to linker, the module is still > not executable on stack. I think that we need this patch to fix up it or > another patch to remove the variable in Makefile if it is not necessary. > Both are fine for me. For now, it i

[PATCH v2 1/2] ARC: setup SMP_CACHE_BYTES and cache_line_size

2018-07-26 Thread Eugeniy Paltsev
As for today we don't setup SMP_CACHE_BYTESi and cache_line_size for ARC, so they are set to L1_CACHE_BYTES by default. L1 line length (L1_CACHE_BYTES) might be easily smaller than L2 line (which is usually the case BTW). This breaks code. For example this breaks ethernet infrastructure on HSDK/AX

[PATCH v2 2/2] ARC: add SMP_CACHE_BYTES value validate

2018-07-26 Thread Eugeniy Paltsev
Check that SMP_CACHE_BYTES (and hence ARCH_DMA_MINALIGN) is larger or equal to any cache line length by comparing it with values previously read from ARC cache BCR registers. Signed-off-by: Eugeniy Paltsev --- Changes v1->v2: * None. arch/arc/mm/cache.c | 10 ++ 1 file changed, 10 inse

[PATCH] NET: stmmac: align DMA stuff to largest cache line length

2018-07-26 Thread Eugeniy Paltsev
As for today STMMAC_ALIGN macro (which is used to align DMA stuff) relies on L1 line length (L1_CACHE_BYTES). This isn't correct in case of system with several cache levels which might have L1 cache line length smaller than L2 line. This can lead to sharing one cache line between DMA buffer and oth

[PATCH 2/2] ARC: add SMP_CACHE_BYTES value validate

2018-07-26 Thread Eugeniy Paltsev
Check that SMP_CACHE_BYTES (and hence ARCH_DMA_MINALIGN) is larger or equal to any cache line length by comparing it with values previously read from ARC cache BCR registers. Signed-off-by: Eugeniy Paltsev --- arch/arc/mm/cache.c | 10 ++ 1 file changed, 10 insertions(+) diff --git a/ar

[PATCH 1/2] ARC: setup SMP_CACHE_BYTES and cache_line_size

2018-07-26 Thread Eugeniy Paltsev
As for today we don't setup SMP_CACHE_BYTESi and cache_line_size for ARC, so they are set to L1_CACHE_BYTES by default. L1 line length (L1_CACHE_BYTES) might be easily smaller than L2 line (which is usually the case BTW). This breaks code. For example this breaks ethernet infrastructure on HSDK/AX

Re: [PATCH 3/4] ARC: refactor arch/arc/mm/dma.c

2018-07-26 Thread Christoph Hellwig
On Tue, Jul 24, 2018 at 01:10:00PM +0300, Eugeniy Paltsev wrote: > Refactoring, no functional change intended. Might be worth explaining a bit why you are refactoring it (i.e. what is the benefit). > > Signed-off-by: Eugeniy Paltsev > --- > arch/arc/mm/dma.c | 28 ++-- >

Re: [PATCH 2/4] ARC: allow to use IOC and non-IOC DMA devices simultaneously

2018-07-26 Thread Christoph Hellwig
> select DMA_NONCOHERENT_OPS > + select DMA_DIRECT_OPS DMA_NONCOHERENT_OPS already selects DMA_DIRECT_OPS. Otherwise looks good: Reviewed-by: Christoph Hellwig ___ linux-snps-arc mailing list linux-snps-arc@lists.infradead.org http://lists.

Re: [PATCH] ARC: fix broken noncoherent cache ops

2018-07-26 Thread Christoph Hellwig
On Tue, Jul 24, 2018 at 05:13:02PM +0300, Eugeniy Paltsev wrote: > All DMA devices on ARC haven't worked with SW cache control > since commit a8eb92d02dd7 ("arc: fix arc_dma_{map,unmap}_page") > This happens because we don't check direction argument at all in > new implementation. Fix that. > > Fi