Hi Mikulas,
On Wed, 2018-06-06 at 11:46 -0400, Mikulas Patocka wrote:
>
> On Wed, 6 Jun 2018, Alexey Brodkin wrote:
>
> > Hi Mikulas,
> >
> > On Tue, 2018-06-05 at 11:30 -0400, Mikulas Patocka wrote:
> > >
> > > On Tue, 5 Jun 2018, Alexey Brodkin wrote:
> > >
> > > > Hi Mikulas,
> > > >
> >
> +#ifndef ASM_ARC_DMA_MAPPING_H
> +#define ASM_ARC_DMA_MAPPING_H
> +
> +#define arch_setup_dma_ops arch_setup_dma_ops
> +
> +#include
> +
> +void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size,
> + const struct iommu_ops *iommu, bool coherent);
Can you keep the
The ARC HS processor provides an IOC port (I/O coherency bus
interface) that allows external devices such as DMA devices
to access memory through the cache hierarchy, providing
coherency between I/O transactions and the complete memory
hierarchy.
Some recent SoC with ARC HS (like HSDK) allow to se
