On 12/09/2017 05:59 AM, Eugeniy Paltsev wrote:
Set initial core pll output frequency on HSDK and AXS103 via
"assigned-clock-rates" property in device tree.
It will be applied at the core pll driver probing.
Eugeniy Paltsev (4):
ARC: [plat-hsdk]: Set initial core pll output frequency
ARC: [
Hi Amitkumar,
On Wed, 2017-12-06 at 12:43 +0530, Amitkumar Karwar wrote:
> On Tue, Dec 5, 2017 at 9:41 PM, Alexey Brodkin
> wrote:
> > Hi Amit,
> >
> > I'm seeing quite a strange behavior of RedPine module.
> > It connects perfectly fine to one of access points but fails
> > to connect to anothe
Hi Prameela,
On Fri, 2017-12-15 at 18:14 +0530, Prameela Rani Garnepudi wrote:
> Hi Alexey,
>
>
> On Friday 15 December 2017 04:50 PM, Alexey Brodkin wrote:
> > Hi Prameela,
> >
> > On Fri, 2017-12-15 at 11:13 +0530, Prameela Rani Garnepudi wrote:
> >> Hi Alexey,
> >>
> >> Please use the
Hi Prameela,
On Fri, 2017-12-15 at 11:13 +0530, Prameela Rani Garnepudi wrote:
> Hi Alexey,
>
> Please use the attached patch to improve TX throughput. We will be
> submitting this patch along with few others soon.
Could you please specify which branch this patch is based on?
I tried to apply
