On 11/27/2017 10:56 AM, Eugeniy Paltsev wrote:
Set initial core pll output frequency on HSDK and AXS103 via
"assigned-clock-rates" property in device tree.
It will be applied at the core pll driver probing.
Can you repost - CC'ing Stephen boyd and RobH ?
-Vineet
Eugeniy Paltsev (4):
ARC:
On 12/03/2017 02:32 PM, Sudip Mukherjee wrote:
On Mon, Nov 27, 2017 at 10:25:16AM -0800, Vineet Gupta wrote:
+CC linux-arch, Arnd
On 11/23/2017 09:17 AM, Alexey Brodkin wrote:
Hi Sudip,
On Tue, 2017-11-21 at 22:10 +, Sudip Mukherjee wrote:
I understand the case/need for adding a weak
