Re: snps, dwmac interrupt storm (Was: ARC770: "unexpected IRQ trap at vector 00" during boot)

2017-08-01 Thread Vineet Gupta
On 08/02/2017 03:03 AM, Alex wrote: On 07/25/2017 08:08 PM, Vineet Gupta wrote: Hi Vineet, On 07/26/2017 01:41 AM, Alexey Brodkin wrote: BTW what is your exact kernel version? In the meantime we'll try to revisit rework of ARC's INTC init procedure but I cannot promise anything very soon as

snps,dwmac interrupt storm (Was: ARC770: "unexpected IRQ trap at vector 00" during boot)

2017-08-01 Thread Alex
On 07/25/2017 08:08 PM, Vineet Gupta wrote: Hi Vineet, On 07/26/2017 01:41 AM, Alexey Brodkin wrote: BTW what is your exact kernel version? In the meantime we'll try to revisit rework of ARC's INTC init procedure but I cannot promise anything very soon as I'm on ETO this week but we'll see h

Re: [PATCH] arc: arcv2: cache: Explicitly set MSB counterpart of region ops addresses

2017-08-01 Thread Vineet Gupta
On 08/01/2017 03:29 PM, Alexey Brodkin wrote: It is necessary to explicitly set both SLC_AUX_RGN_START1 and SLC_AUX_RGN_END1 which hold MSB bits of the physical address correspondingly of region start and end otherwise SLC region operation is executed in unpredictable manner, for example on HSDK

[PATCH] arc: arcv2: cache: Explicitly set MSB counterpart of region ops addresses

2017-08-01 Thread Alexey Brodkin
It is necessary to explicitly set both SLC_AUX_RGN_START1 and SLC_AUX_RGN_END1 which hold MSB bits of the physical address correspondingly of region start and end otherwise SLC region operation is executed in unpredictable manner, for example on HSDK platform where PAE40 support exists in hardware