On 06/08/2017 11:23 AM, Noam Camus wrote:
*> From:* Vineet Gupta
*> Sent:* Thursday, June 8, 2017 7:38 PM
>>
>> With simulator we just turn this configuration on, so we redirect the Legacy
>> Synopsys L2 ISR from nSIM into machine check.
>> This way we end up just like with silicon 😊
>This
On Thu, Jun 08, 2017 at 09:31:54AM -0700, Vineet Gupta wrote:
> On 06/08/2017 09:10 AM, Krzysztof Kozlowski wrote:
> > Remove old, dead Kconfig option INET_LRO. It is gone since
> > commit 7bbf3cae65b6 ("ipv4: Remove inet_lro library").
> >
> > Signed-off-by: Krzysztof Kozlowski
>
> Acked-by: vi
On 06/07/2017 08:29 PM, Noam Camus wrote:
*From:* Noam Camus
*Sent:* Wednesday, June 7, 2017 8:06:17 PM
*To:* Vineet Gupta; linux-snps-arc@lists.infradead.org
*Cc:* linux-ker...@vger.kernel.org; Elad Kanfi
*Subject:* Re: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an
exception
*>
On 06/08/2017 09:10 AM, Krzysztof Kozlowski wrote:
Remove old, dead Kconfig option INET_LRO. It is gone since
commit 7bbf3cae65b6 ("ipv4: Remove inet_lro library").
Signed-off-by: Krzysztof Kozlowski
Acked-by: vineet Gupta
Do you want me to pick this up via ARC tree ?
Thx,
-Vineet
_
Remove old, dead Kconfig option INET_LRO. It is gone since
commit 7bbf3cae65b6 ("ipv4: Remove inet_lro library").
Signed-off-by: Krzysztof Kozlowski
---
arch/arc/configs/nps_defconfig | 1 -
arch/arc/configs/tb10x_defconfig | 1 -
2 files changed, 2 deletions(-)
diff --git a/arch/arc/configs/
Hi,
While cleaning Samsung ARM defconfigs with savedefconfig, I encountered
similar obsolete entries in other files.
Except the ARM, no dependencies.
For ARM, the rest of patches depend on the first change (otherwise
it might not apply cleanly).
Best regards,
Krzysztof
Krzysztof Kozlowski (35)
We faced with problem when we tried to utilize 1G DRAM by linux on
HSDK.
We can't use our usual kernel memory address (0x8000) like on
AXS103 because of DCCM memory bank located at exactly same
address (0x8000)
But we can't simply move kernel memory address to another address (like
0x9
From: Noam Camus
Working with NPS400 we noticed that there is a possibility of L1
interrupt nesting that may run out kernel stack.
The scenario include serving invoke_softirqs() from irq_exit()
and once local_irq_enable() called can hit another one before we
managed to restore last one and pop so
From: Noam Camus
The reasons are:
1) speeding up boot time, becomes critical for many CPUs machine,
e.g. NPS400 with 4K CPUs
2) shorten kernel log at boot time, again easy to scan for large
scale machines such NPS400
Signed-off-by: Noam Camus
---
arch/arc/kernel/setup.c |6 +++---
ar
From: Elad Kanfi
HW bug description: in case of HW thread context switch
the dpc configuration of the exiting thread is dragged
one cycle into the next thread.
In order to avoid the consequences of this bug, the DPC register
is set to an initial value, and not changed afterwards.
Signed-off-by:
From: Noam Camus
With this patch set I continue the effort of upstreaming the eznps platform for
arch/arc.
It comprise of couple of patches from last set yet not accepted,
patches for HW erratas and some misc extensions such for HIGHMEM / NUMA.
This set got more generic ARC changes than previo
From: Noam Camus
This is needed for NPS400 where high memory is assigned to node1
where the associated addresses are lower than node0.
This use case is not typical and just using discontigmem is not enough
since nodes assumed to have increasing address range.
i.e. address range of node0 assumed t
From: Noam Camus
thread_struct got new field for data plane of eznps platform.
This field got place for data plane auxiliary registers and for
any extra registers that might be changed in kernel code.
We save EFLAGS, and GPA1 auxiliary registers since they may be
changed by the new task while us
From: Liav Rehana
Preserve eflags and gpa1 auxiliaries during exception
Registers used by compare exchange instructions.
GPA1 is used for compare value, and EFLAGS got bit reflects
atomic operation response.
EFLAGS is zeroed for each new user task so it won't get its
parent value.
Signed-off-by
From: Noam Camus
We add ability for all cores at NPS SoC to control the number of cycles
HW thread can execute before it is replace with another eligible
HW thread within the same core. The replacement is done by the
HE scheduler.
Signed-off-by: Noam Camus
---
Documentation/admin-guide/kernel-
From: Noam Camus
This way FIXMAP can have 2 PTEs per CPU even for
NR_CPUS=4096
For the extreme case like in eznps platform We use
all gutter between kernel and user.
Signed-off-by: Noam Camus
---
arch/arc/Kconfig | 11 +++
arch/arc/include/asm/highmem.h |8
From: Noam Camus
Now it is used for NPS SoC for multi-core of 256 cores
and SMT of 16 HW threads per core.
This way with topology the scheduler is much efficient in
creating domains and later using them.
Signed-off-by: Noam Camus
---
arch/arc/Kconfig| 27
arch/arc/i
From: Noam Camus
This patch is derived due to performance issue.
The use case is a page fault that resides on more than the local cpu.
Trying to broadcast all CPUs results on performance degradation.
So we try to avoid this by sending only to the relevant CPUs.
Signed-off-by: Noam Camus
Reviewe
From: Liav Rehana
The following commit adds a config that will enable us to distinguish
between building the kernel for platforms that have a different set
of auxiliary registers for each cpu and platforms that have a shared
set of auxiliary registers across every thread in each core.
On platform
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