On Monday 18 April 2016 04:00 PM, Jose Abreu wrote:
>>> + if (readl((void *)FPGA_VER_INFO) <= FPGA_VER_27M) {
>> > Please don't readl directly from addresses. I think I mentioned
>> > that before and didn't get back to you when you replied asking
>> > for other solutions. I still think a proper D
Hi Stephen,
On 16-04-2016 00:46, Stephen Boyd wrote:
> On 04/11, Jose Abreu wrote:
>> new file mode 100644
>> index 000..3ba4e2f
>> --- /dev/null
>> +++ b/drivers/clk/axs10x/i2s_pll_clock.c
>> @@ -0,0 +1,217 @@
>> +
>> +static int i2s_pll_clk_probe(struct platform_device *pdev)
>> +{
>> +
On 18/04/16 07:51, Vineet Gupta wrote:
> Hi Marc,
>
> On Wednesday 13 April 2016 05:10 PM, Vineet Gupta wrote:
>> Now that we have Timers probed from DT, don't need legacy domain
>>
>> This however requires mapping to be called explicitly for the IRQ which
>> still can't (and probably never) be pr
On Mon, Apr 18, 2016 at 12:16:10PM +0530, Vineet Gupta wrote:
> - timer frequency is derived from DT (no longer rely on top level
>DT "clock-frequency" probed early and exported by asm/clk.h)
>
> - TIMER0_IRQ need not be exported across arch code, confined to intc as
>it is property of s
