From: Noam Camus
Change Log--
v8:
Change macro name from IPI_IRQ to NPS_IPI_IRQ.
This was needed due to build warning when building for parsic.
v7:
Rebased on latest HEAD (4.6-rc1)
Added change log to all patches to ease review.
v6:
Files headers changed to start with:
Copyright (c) 2016, Mella
From: Noam Camus
This header file is for NPS400 SoC.
It includes macros for accessing memory mapped registers.
These are functional registers that core can use to configure SoC.
Signed-off-by: Noam Camus
Cc: Daniel Lezcano
Cc: Vineet Gupta
---
v8:
Change macro name from IPI_IRQ to NPS_IPI_IRQ
From: Noam Camus
Add internal tick generator which is shared by all cores.
Each cluster of cores view it through dedicated address.
This is used for SMP system where all CPUs synced by same
clock source.
Signed-off-by: Noam Camus
Cc: Daniel Lezcano
Cc: Rob Herring
Cc: Thomas Gleixner
Cc: Joh
From: Noam Camus
Adding EZchip NPS400 support.
Internal interrupts are handled by Multi Thread Manager (MTM)
Once interrupt is serviced MTM is acked for deactivating the interrupt.
External interrupts are handled by MTM as well as at Global Interrupt
Controller (GIC) e.g. serial and network devic
OK linus/axs101_defconfig/arcompact Mon Apr 04, 04:01
http://kisskb.ellerman.id.au/kisskb/buildresult/12653240/
Commit: Linux 4.6-rc2
9735a22799b9214d17d3c231fe377fc852f042e9
Compiler: arc-buildroot-linux-uclibc-gcc (Buildroot 2015.08.1) 4.8.4
No errors found in log
Possible warning