23]
>url:
>https://github.com/0day-ci/linux/commits/Noam-Camus/Adding-plat-eznps-to-ARC/20151227-220433
>base: https://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc for-next
>config: i386-allmodconfig (attached as .config)
>reproduce:
> # save the attached .config to
From: Noam Camus
This commit should be left last since only now eznps platform
is in state which one can actually use.
Signed-off-by: Noam Camus
---
arch/arc/Kconfig |1 +
arch/arc/Makefile |5 +
2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/arc/Kconfig b/arch
From: Tal Zilcer
Since the CTOP is SMT hardware multi-threaded, we need to hint
the HW that now will be a very good time to do a hardware
thread context switching. This is done by issuing the schd.rw
instruction (binary coded here so as to not require specific
revision of GCC to build the kernel)
From: Noam Camus
The default 256 bytes sometimes is just not enough.
We usually provide earlycon=... and console=... and ip=...
All this and more may need more room.
Signed-off-by: Noam Camus
Acked-by: Vineet Gupta
---
arch/arc/include/asm/setup.h |4
1 files changed, 4 insertions(+)
From: Noam Camus
With generic "identity" num of CPUs is limited to 256 (8 bit).
We use our alternative AUX register GLOBAL_ID (12 bit).
Now we can support up to 4096 CPUs.
Signed-off-by: Noam Camus
---
arch/arc/include/asm/entry-compact.h |8
arch/arc/kernel/ctx_sw.c |
From: Noam Camus
We need our own implementaions since we lack LLSC support.
Our extended ISA provided with optimized solution for all 32bit
operations we see in these three headers.
Signed-off-by: Noam Camus
---
arch/arc/include/asm/atomic.h | 79 +++-
arch/ar
From: Noam Camus
NPS use special mapping right below TASK_SIZE.
Hence we need to lower STACK_TOP so that user stack won't
overlap NPS special mapping.
Signed-off-by: Noam Camus
Acked-by: Vineet Gupta
---
arch/arc/include/asm/processor.h | 17 +
arch/arc/mm/tlb.c
From: Noam Camus
NPS device got 256 cores and each got 16 HW threads (SMT).
We use EZchip dedicated ISA to trigger HW scheduler of the
core that current HW thread belongs to.
This scheduling makes sure that data beyond barrier is available
to all HW threads in core and by that to all in device (4
From: Noam Camus
This platform include boards:
Hardware Emulator (HE)
Simulator based upon nSIM.
Signed-off-by: Noam Camus
---
MAINTAINERS |6 +
arch/arc/plat-eznps/Kconfig | 34 ++
arch/arc/plat-eznps/Makefile|7
From: Noam Camus
Adding default configuration file and DTS file
Signed-off-by: Noam Camus
---
arch/arc/boot/dts/eznps.dts| 94
arch/arc/configs/nps_defconfig | 85
2 files changed, 179 insertions(+), 0 deleti
From: Noam Camus
ARC uses hwirq at arch_do_IRQ() to pass into generic_handle_irq().
This is wrong since we need first to reverse map it into virq.
Happily, if we use handle_domain_irq() we get all we need.
Just like ARM I created a pointer to handler that should be filled
by an interrupt contro
From: Noam Camus
This behaviour is the desired one as been seen on other arch's.
We do not use generic irq domain and hence hwirq number is used
directly by our code without any mapping to virq.
In order to add IPI status to /proc/interrupts we use
hardirq macros also we define arch_show_interru
From: Noam Camus
In SMP setup, master loops for each_present_cpu calling cpu_up().
For ARC it returns as soon as new cpu's status becomes online,
However secondary may still do HW initializing,
machine or platform hook level.
So turn secondary online only after all HW setup is done.
Signed-off-b
From: Noam Camus
We've designated:
TIMER0 for events (clockevents)
TIMER1 for free running (clocksource)
Till now timer configuration was done on arch/arc/kernel/time.c
with constant values.
This commit add device tree support so we can do this work
at dedicated clocksource driver which parse t
From: Noam Camus
User space use lower 2G of the virtual address space.
However kernel steals upper 512M of this space.
This stolen space is used partially for vmalloc and the rest
serves as gutter between kernel and user space.
The vmalloc size is depend on NR_CPUS since "per cpu" mechanism
use v
From: Noam Camus
Add internal tick generator which is shared by all cores.
Each cluster of cores view it through dedicated address.
This is used for SMP system where all CPUs synced by same
clock source.
Signed-off-by: Noam Camus
Cc: Daniel Lezcano
Cc: Rob Herring
Cc: Thomas Gleixner
Cc: Joh
From: Noam Camus
If we hold rwlock and interrupt occures we may
end up spinning on it for ever during softirq.
Note that this lock is an internal lock
and since the lock is free to be used from any context,
the lock needs to be IRQ-safe.
Below you may see an example for interrupt we get while
nl
From: Noam Camus
Adding EZchip NPS400 support.
NPS internal interrupts are internally handled at
Multi Thread Manager (MTM) that is signaled for deactivating
an interrupt.
External interrupts is handled also at Global Interrupt
Controller (GIC) e.g. serial and network devices.
Signed-off-by: Noa
From: Noam Camus
We add IPI irq definition to be used later by any
irqchip such NPS400 IC.
Signed-off-by: Noam Camus
---
arch/arc/include/asm/irq.h |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/arc/include/asm/irq.h b/arch/arc/include/asm/irq.h
index 4fd7d62.
From: Noam Camus
This header file is for NPS400 SoC.
It includes macros for accessing memory mapped registers.
These are functional registers that core can use to configure SoC.
Signed-off-by: Noam Camus
---
include/soc/nps/common.h | 123 ++
1 file
From: Noam Camus
Add EZchip to vendor prefixes list.
EZchip introduce the NPS platform for the ARC architecture.
Signed-off-by: Noam Camus
Acked-by: Rob Herring
Cc: Pawel Moll
---
Documentation/devicetree/bindings/arc/eznps.txt|7 +++
.../devicetree/bindings/vendor-prefixes.txt
From: Noam Camus
v5:
1) irqchip -- work with handle_domain_irq(), and remove use of
irq_set_default_host()
2) clocksource -- initialize clockevents as well by parsing interrupts node of
DT
3) Do not use IPI with irq generic infrastructure
v4:
1) irqchip -- use irq_domain_add_linear()
2) clocks
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