On Wednesday 02 December 2015 01:09 AM, Carlos Palminha wrote:
> Hi guys,
>
> I'm bringing up a new ARC PGU driver for DRM framework with latest kernel
> tree.
> I'm using ARC AXS101 as a base and selected one the DRM required config:
> HAVE_DMA_ATTRS due to some memory allocation helpers in DRM.
Hi guys,
I'm bringing up a new ARC PGU driver for DRM framework with latest kernel tree.
I'm using ARC AXS101 as a base and selected one the DRM required config:
HAVE_DMA_ATTRS due to some memory allocation helpers in DRM.
I'm getting some errors with DMA functions not implemented in ARC:
dma_a
On 01/12/15 13:02, Noam Camus wrote:
> From: Noam Camus
>
> Adding EZchip NPS400 support.
> NPS internal interrupts are internally handled at
> Multi Thread Manager (MTM) that is signaled for deactivating
> an interrupt.
> External interrupts is handled also at Global Interrupt
> Controller (GIC)
From: Noam Camus
This commit should be left last since only now eznps platform
is in state which one can actually use.
Signed-off-by: Noam Camus
---
arch/arc/Kconfig |1 +
arch/arc/Makefile |5 +
2 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/arch/arc/Kconfig b/arch
From: Noam Camus
The default 256 bytes sometimes is just not enough.
We usually provide earlycon=... and console=... and ip=...
All this and more may need more room.
Signed-off-by: Noam Camus
Acked-by: Vineet Gupta
---
arch/arc/include/asm/setup.h |4
1 files changed, 4 insertions(+)
From: Noam Camus
With generic "identity" num of CPUs is limited to 256 (8 bit).
We use our alternative AUX register GLOBAL_ID (12 bit).
Now we can support up to 4096 CPUs.
Signed-off-by: Noam Camus
---
arch/arc/include/asm/entry-compact.h |8
arch/arc/kernel/ctx_sw.c |
From: Tal Zilcer
Since the CTOP is SMT hardware multi-threaded, we need to hint
the HW that now will be a very good time to do a hardware
thread context switching. This is done by issuing the schd.rw
instruction (binary coded here so as to not require specific
revision of GCC to build the kernel)
From: Noam Camus
NPS device got 256 cores and each got 16 HW threads (SMT).
We use EZchip dedicated ISA to trigger HW scheduler of the
core that current HW thread belongs to.
This scheduling makes sure that data beyond barrier is available
to all HW threads in core and by that to all in device (4
From: Noam Camus
This platform include boards:
Hardware Emulator (HE)
Simulator based upon nSIM.
Signed-off-by: Noam Camus
---
MAINTAINERS |6 +
arch/arc/plat-eznps/Kconfig | 34
arch/arc/plat-eznps/Makefile|7 +
From: Noam Camus
Adding default configuration file and DTS file
Signed-off-by: Noam Camus
---
arch/arc/boot/dts/eznps.dts| 76 +++
arch/arc/configs/nps_defconfig | 85
2 files changed, 161 insertions(+), 0 deletio
From: Noam Camus
We need our own implementaions since we lack LLSC support.
Our extended ISA provided with optimized solution for all 32bit
operations we see in these three headers.
Signed-off-by: Noam Camus
---
arch/arc/include/asm/atomic.h | 79 +++-
arch/ar
From: Noam Camus
NPS use special mapping right below TASK_SIZE.
Hence we need to lower STACK_TOP so that user stack won't
overlap NPS special mapping.
Signed-off-by: Noam Camus
Acked-by: Vineet Gupta
---
arch/arc/include/asm/processor.h | 17 +
arch/arc/mm/tlb.c
From: Noam Camus
External clock source can be used if included by one of
DTS file of a chosen platform.
Signed-off-by: Noam Camus
Acked-by: Vineet Gupta
---
arch/arc/kernel/time.c |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/arc/kernel/time.c b/arch/arc/ker
From: Noam Camus
This will better reflect its description i.e. "any needed setup..."
and not just do an "IPI request".
Signed-off-by: Noam Camus
Acked-by: Vineet Gupta
---
arch/arc/include/asm/smp.h |4 ++--
arch/arc/kernel/irq.c |4 ++--
arch/arc/kernel/mcip.c |2 +-
arc
From: Noam Camus
User space use lower 2G of the virtual address space.
However kernel steals upper 512M of this space.
This stolen space is used partially for vmalloc and the rest
serves as gutter between kernel and user space.
The vmalloc size is depend on NR_CPUS since "per cpu" mechanism
use v
From: Noam Camus
v3:
1) irqchip: use MACROS instead of structures to decribe
registers.
2) clocksource: use 32bit counter and avoid 2 halfs read
of 64bit dance.
v2:
1) Remove out of tree platform include path
2) Move atomic/bitop/cmpxchg for platform to end.
From: Noam Camus
Adding EZchip NPS400 support.
NPS internal interrupts are internally handled at
Multi Thread Manager (MTM) that is signaled for deactivating
an interrupt.
External interrupts is handled also at Global Interrupt
Controller (GIC) e.g. serial and network devices.
Signed-off-by: Noa
From: Noam Camus
We add IPI irq definition to be used later by any
irqchip such NPS400 IC.
Signed-off-by: Noam Camus
---
arch/arc/include/asm/irq.h |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/arc/include/asm/irq.h b/arch/arc/include/asm/irq.h
index 4fd7d62.
From: Noam Camus
In SMP setup, master loops for each_present_cpu calling cpu_up().
For ARC it returns as soon as new cpu's status becomes online,
However secondary may still do HW initializing,
machine or platform hook level.
So turn secondary online only after all HW setup is done.
Signed-off-b
From: Noam Camus
If we hold rwlock and interrupt occures we may
end up spinning on it for ever during softirq.
Note that this lock is an internal lock
and since the lock is free to be used from any context,
the lock needs to be IRQ-safe.
Below you may see an example for interrupt we get while
nl
From: Noam Camus
Add internal tick generator which is shared by all cores.
Each cluster of cores view it through dedicated address.
This is used for SMP system where all CPUs synced by same
clock source.
Signed-off-by: Noam Camus
Cc: Daniel Lezcano
Cc: Rob Herring
Cc: Thomas Gleixner
Cc: Joh
From: Noam Camus
Add EZchip to vendor prefixes list.
EZchip introduce the NPS platform for the ARC architecture.
Signed-off-by: Noam Camus
Acked-by: Rob Herring
Cc: Pawel Moll
---
Documentation/devicetree/bindings/arc/eznps.txt|7 +++
.../devicetree/bindings/vendor-prefixes.txt
Hi,
Please add upstream commit 30b9dbee895ff ("ARC: Fix silly typo in MAINTAINERS
file") to stable releases.
This depends on 9acdc911b55569145 ("MAINTAINERS: Add public mailing list for
ARC")
which was already marked for stable inclusion and is hitting the stable trees
ATM.
Thx,
-Vineet
_
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