On 05/25/2018 05:26 PM, Hans Verkuil wrote:
> On 25/05/18 16:16, Sakari Ailus wrote:
>> Hi Hans,
>>
>> On Thu, May 24, 2018 at 10:44:13AM +0200, Hans Verkuil wrote:
>>> Memory-to-memory devices have one video node, one internal control handler
>>> but two vb2_queues (DMA engines). While often there
On 25/05/18 16:16, Sakari Ailus wrote:
> Hi Hans,
>
> On Thu, May 24, 2018 at 10:44:13AM +0200, Hans Verkuil wrote:
>> Memory-to-memory devices have one video node, one internal control handler
>> but two vb2_queues (DMA engines). While often there is one buffer produced
>> for every buffer consum
On Fri, May 25, 2018 at 11:17 PM Sakari Ailus
wrote:
> Hi Hans,
> On Thu, May 24, 2018 at 10:44:13AM +0200, Hans Verkuil wrote:
> > Memory-to-memory devices have one video node, one internal control
handler
> > but two vb2_queues (DMA engines). While often there is one buffer
produced
> > for ev
Hi Hans,
On Thu, May 24, 2018 at 10:44:13AM +0200, Hans Verkuil wrote:
> Memory-to-memory devices have one video node, one internal control handler
> but two vb2_queues (DMA engines). While often there is one buffer produced
> for every buffer consumed, but this is by no means standard. E.g.
> de
On Thu, May 24, 2018 at 5:44 PM Hans Verkuil wrote:
> Memory-to-memory devices have one video node, one internal control handler
> but two vb2_queues (DMA engines). While often there is one buffer produced
> for every buffer consumed, but this is by no means standard. E.g.
deinterlacers
> will pr
Memory-to-memory devices have one video node, one internal control handler
but two vb2_queues (DMA engines). While often there is one buffer produced
for every buffer consumed, but this is by no means standard. E.g. deinterlacers
will produce on buffer for every two buffers consumed. Codecs that re
