This message is generated daily by a cron job that builds media_tree for
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Results of the daily build of media_tree:
date: Sat Jun 23 05:00:18 CEST 2018
media-tree git hash:f2809d20b9250c675fca8268a0f6274277cca7ff
media_build gi
Hi Philipp,
I love your patch! Perhaps something to improve:
[auto build test WARNING on linus/master]
[also build test WARNING on v4.18-rc1 next-20180622]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci
> And I think you may missed to create a cover page. Please follow my BKM.
> Thanks.
> git format-patch --cover --subject-prefix -o HEAD~n
-v will do the job in a less error prone way.
Le vendredi 22 juin 2018 à 17:52 +0200, Philipp Zabel a écrit :
> Add a single imx-media mem2mem video device that uses the IPU IC PP
> (image converter post processing) task for scaling and colorspace
> conversion.
> On i.MX6Q/DL SoCs with two IPUs currently only the first IPU is used.
>
> The ha
You can add my Acked-by: Jasmin Jessich
On 06/19/2018 08:51 PM, Daniel Scheller wrote:
> From: Daniel Scheller
>
> There's a superfluous whitespace in the boilerplate license text in both
> .c and .h files. Fix this.
>
> Cc: Ralph Metzler
> Cc: Manfred Voelkel
> Signed-off-by: Daniel Schelle
You can add my Acked-by: Jasmin Jessich
On 06/19/2018 08:51 PM, Daniel Scheller wrote:
> From: Daniel Scheller
>
> In commit 3db30defab4b ("use correct MODULE_LINCESE for GPL v2 only
> according to notice in header") in the upstream repository for the
> mentioned driver at https://github.com/Di
You can add my Acked-by: Jasmin Jessich
On 06/19/2018 08:51 PM, Daniel Scheller wrote:
> From: Daniel Scheller
>
> As both the MODULE_LICENSE and the boilerplates are now in sync and clear
> that the driver is licensed under the terms of the GPLv2-only, add a
> matching SPDX license identifier
On Fri, 2018-06-22 at 08:58 +0200, Hans Verkuil wrote:
> On 06/21/2018 10:38 PM, Ezequiel Garcia wrote:
> > A memory-to-memory pipeline device consists in three
> > entities: two DMA engine and one video processing entities.
> > The DMA engine entities are linked to a V4L interface.
> >
> > This c
Store tile top/left position in pixels in the tile structure.
This will allow overlapping tiles with different sizes later.
Signed-off-by: Philipp Zabel
---
drivers/gpu/ipu-v3/ipu-image-convert.c | 27 ++
1 file changed, 15 insertions(+), 12 deletions(-)
diff --git a/dri
This will allow to calculate seam positions after initializing the
ipu_image base structure but before calculating tile dimensions.
Signed-off-by: Philipp Zabel
---
drivers/gpu/ipu-v3/ipu-image-convert.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/drive
Move tile_width_align and tile_height_align up so they
can be used by the tile edge position calculation code.
Signed-off-by: Philipp Zabel
---
drivers/gpu/ipu-v3/ipu-image-convert.c | 54 +-
1 file changed, 27 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/ipu-
Let convert_start start from a given tile index, allocate intermediate
tile with maximum tile size.
Signed-off-by: Philipp Zabel
---
drivers/gpu/ipu-v3/ipu-image-convert.c | 60 +++---
1 file changed, 35 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/ipu-v3/ipu-imag
If we allow different tile sizes, the output tile with / height
alignment doesn't need to be multiplied by number of columns / rows.
Signed-off-by: Philipp Zabel
---
drivers/gpu/ipu-v3/ipu-image-convert.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/ipu-v3
Add a single imx-media mem2mem video device that uses the IPU IC PP
(image converter post processing) task for scaling and colorspace
conversion.
On i.MX6Q/DL SoCs with two IPUs currently only the first IPU is used.
The hardware only supports writing to destination buffers up to
1024x1024 pixels i
Select seam positions that minimize distortions during seam hiding while
satifying input and output IDMAC, rotator, and image format constraints.
This code looks for aligned output seam positions that minimize the
difference between the fractional corresponding ideal input positions
and the input
Slightly modifying resize coefficients per-tile allows to completely
hide the seams between tiles and to sample the correct input pixels at
the bottom and right edges of the image.
Tiling requires a bilinear interpolator reset at each tile start, which
causes the image to be slightly shifted if th
For tiled scaling, we want to compute the scaling coefficients
externally in such a way that the interpolation overshoots tile
boundaries and samples up to the first pixel of the next tile.
Prepare to override the resizing coefficients from the image
conversion code.
Signed-off-by: Philipp Zabel
Since tile dimensions now vary between tiles, add debug output for each
tile's position and dimensions.
Signed-off-by: Philipp Zabel
---
drivers/gpu/ipu-v3/ipu-image-convert.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/ipu-v3/ipu-image-convert.c
Hi,
we have image conversion code for scaling and colorspace conversion in
the IPUv3 base driver for a while. Since the IC hardware can only write
up to 1024x1024 pixel buffers, it scales to larger output buffers by
splitting the input and output frame into similarly sized tiles.
This causes the
If we allow the 8-pixel DMA bursts to overshoot the end of the line, the
only input alignment restrictions are dictated by the pixel format and
8-byte aligned line start address.
Signed-off-by: Philipp Zabel
---
drivers/gpu/ipu-v3/ipu-image-convert.c | 7 ---
1 file changed, 7 deletions(-)
Double-buffering only works if tile sizes are the same and the resizing
coefficient does not change between tiles, even for non-planar formats.
Signed-off-by: Philipp Zabel
---
drivers/gpu/ipu-v3/ipu-image-convert.c | 27 --
1 file changed, 25 insertions(+), 2 deletions(-
For the planar but U/V-packed formats NV12 and NV16, 8 pixel width
alignment is good enough to fulfill the 8 byte stride requirement.
Signed-off-by: Philipp Zabel
---
drivers/gpu/ipu-v3/ipu-image-convert.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/ipu-v3/ipu
For differently sized tiles or if the resizing coefficients change,
we have to stop, reconfigure, and restart the IC between tiles.
Signed-off-by: Philipp Zabel
---
drivers/gpu/ipu-v3/ipu-image-convert.c | 65 +-
1 file changed, 44 insertions(+), 21 deletions(-)
diff --g
Visualize the scaling and rotation pipeline with some ASCII art
diagrams. Remove the FIXME comment about missing seam prevention.
Signed-off-by: Philipp Zabel
---
drivers/gpu/ipu-v3/ipu-image-convert.c | 39 +++---
1 file changed, 29 insertions(+), 10 deletions(-)
diff --git
For planar formats, bytesperline does not depend on BPP. It must always
be larger than width and aligned to tile width alignment restrictions.
Signed-off-by: Philipp Zabel
---
drivers/gpu/ipu-v3/ipu-image-convert.c | 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff --
On 22/06/18 01:49, safocl wrote:
> This patch makes it impossible to configure the exposure on webcams,
> specifically a4tech, with others was not checked. Seen from several users.
> link to the Russian forum archlinux:
> https://archlinux.org.ru/forum/topic/18581/?page=1
>
> was checked on webc
Hi Alan,
Thanks for the patch set.
You should change the subject as below.
[PATCH v1, 1/2]
[PATCH v1, 2/2]
And I think you may missed to create a cover page. Please follow my BKM. Thanks.
git format-patch --cover --subject-prefix -o HEAD~n
Regards, Andy
> -Original Message-
> From: C
Hi Laurent,
6.5 weeks and counting. Can we please schedule a review of these patches
for the next week? Not much time is left to make it for 4.19.
Thanks
Guennadi
On Thu, 31 May 2018, Guennadi Liakhovetski wrote:
> Hi Laurent,
>
> More than 3 weeks since v8 has been posted. Seems like we've m
If info->pdata is NULL then we would oops on the next line. And we can
flip the "ret" test around and give up if a failure has already occured.
Signed-off-by: Dan Carpenter
diff --git a/drivers/media/i2c/sr030pc30.c b/drivers/media/i2c/sr030pc30.c
index 2a4882cddc51..4ebd00198d34 100644
--- a/d
From: "alanx.chiang"
Provide a flexible way to determine the addressing bits of eeprom.
It doesn't need to add acpi or i2c ids for specific modules.
Signed-off-by: Alan Chiang
Signed-off-by: Andy Yeh
Reviewed-by: Sakari Ailus
Reviewed-by: Andy Shevchenko
Reviewed-by: Rajmohan Mani
---
driv
From: "alanx.chiang"
The AT24 series chips use 8-bit address by default. If some
chips would like to support more than 8 bits, the at24 driver
should be added the compatible field for specfic chips.
Provide a flexible way to determine the addressing bits through
address-width in this patch.
Sig
Hi,
I found it strange that the macros V4L2_CID_USER_MAX217X_BASE and
V4L2_CID_USER_IMX_BASE have equal value even though each of them state
that they reserved a range. Those reservations look conflicting to me.
The macro V4L2_CID_USER_MAX217X_BASE came first, and
V4L2_CID_USER_IMX_BASE was intro
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