On Wed, Oct 19, 2016 at 01:57:45PM +, Tudor-Dan Ambarus wrote:
Please wrap your mails within 80 chars, I have reflown below for reabability.
> Hi, Herbert,
>
> CAAM has the ability to provide DMA services. This is helpful for
> platforms that don't have a dedicated DMA hardware block.
>
> I
On Thu, Feb 02, 2017 at 10:17:15AM +0530, Anup Patel wrote:
> +config BCM_SBA_RAID
> +tristate "Broadcom SBA RAID engine support"
> +depends on (ARM64 && MAILBOX && RAID6_PQ) || COMPILE_TEST
> +select DMA_ENGINE
> +select DMA_ENGINE_RAID
> + select ASYNC_TX_ENABL
On Mon, Feb 06, 2017 at 05:31:15PM +0530, Anup Patel wrote:
> >> +
> >> +/* SBA C_MDATA helper macros */
> >> +#define SBA_C_MDATA_LOAD_VAL(__bnum0)((__bnum0) & 0x3)
> >> +#define SBA_C_MDATA_WRITE_VAL(__bnum0) ((__bnum0) & 0x3)
> >> +#define SBA_C_MDATA_XOR_VAL(__bnu
On Tue, Feb 07, 2017 at 02:32:15PM +0530, Anup Patel wrote:
> On Tue, Feb 7, 2017 at 1:57 PM, Dan Williams wrote:
> > On Tue, Feb 7, 2017 at 12:16 AM, Anup Patel wrote:
> >> The DMAENGINE framework assumes that if PQ offload is supported by a
> >> DMA device then all 256 PQ coefficients are suppo
On Fri, Oct 27, 2017 at 12:20:32PM +, Horia Geantă wrote:
> On 10/27/2017 2:36 PM, Koul, Vinod wrote:
> >> On 10/26/2017 1:01 PM, Radu Alexe wrote:
> >>> This patch-set introduces a new DMA memcpy driver based on the DMA
> >>> capabilities of the CAAM crypto engine. Because of this dependency t
On Mon, Oct 30, 2017 at 03:46:54PM +0200, Horia Geantă wrote:
> @@ -600,6 +600,23 @@ config ZX_DMA
> help
> Support the DMA engine for ZTE ZX family platform devices.
>
> +config CRYPTO_DEV_FSL_CAAM_DMA
File is sorted alphabetically
> + tristate "CAAM DMA engine support"
> +
On Wed, Nov 08, 2017 at 02:36:31PM +, Radu Andrei Alexe wrote:
> On 10/31/2017 2:01 PM, Vinod Koul wrote:
> > On Mon, Oct 30, 2017 at 03:46:54PM +0200, Horia Geantă wrote:
> >> +/*
> >> + * caam support for SG DMA
> >> + *
> >> + * Copyright 2016 Fr
On Fri, Nov 10, 2017 at 08:02:01AM +, Radu Andrei Alexe wrote:
> On 11/9/2017 6:34 PM, Kim Phillips wrote:
> > On Thu, 9 Nov 2017 11:54:13 +
> > Radu Andrei Alexe wrote:
> >
> >> On 10/30/2017 4:24 PM, Kim Phillips wrote:
> >>> On Mon, 30 Oct 2017 15:46:51 +0200
> >>> Horia Geantă wrote:
On Fri, Nov 10, 2017 at 10:44:30AM -0600, Kim Phillips wrote:
> On Fri, 10 Nov 2017 08:02:01 +
> Radu Andrei Alexe wrote:
>
> > On 11/9/2017 6:34 PM, Kim Phillips wrote:
> > > On Thu, 9 Nov 2017 11:54:13 +
> > > Radu Andrei Alexe wrote:
> > >> The next patch version will create the platf
On Tue, Mar 01, 2016 at 10:54:50PM +0900, Joonsoo Kim wrote:
> 2016-03-01 3:04 GMT+09:00 Dan Williams :
> > On Mon, Feb 29, 2016 at 1:33 AM, Arnd Bergmann wrote:
> >> The addition of tracepoints to the page reference tracking had an
> >> unfortunate side-effect in at least one driver that calls pu
On Fri, Apr 29, 2016 at 10:09:07PM +0200, Julia Lawall wrote:
> Dma_pool_zalloc combines dma_pool_alloc and memset 0. The semantic patch
> that makes this transformation is as follows: (http://coccinelle.lip6.fr/)
Applied all dmaengine patches
--
~Vinod
--
To unsubscribe from this list: send th
On Tue, May 26, 2015 at 04:25:57PM +0300, Peter Ujfalusi wrote:
> dma_request_slave_channel_compat() 'eats' up the returned error codes which
> prevents drivers using the compat call to be able to do deferred probing.
>
> The new wrapper is identical in functionality but it will return with error
On Fri, May 29, 2015 at 11:42:27AM +0200, Geert Uytterhoeven wrote:
> On Fri, May 29, 2015 at 11:33 AM, Vinod Koul wrote:
> > On Tue, May 26, 2015 at 04:25:57PM +0300, Peter Ujfalusi wrote:
> >> dma_request_slave_channel_compat() 'eats' up the returned error codes
On Fri, May 29, 2015 at 05:32:50PM +0300, Peter Ujfalusi wrote:
> On 05/29/2015 01:18 PM, Vinod Koul wrote:
> > On Fri, May 29, 2015 at 11:42:27AM +0200, Geert Uytterhoeven wrote:
> >> On Fri, May 29, 2015 at 11:33 AM, Vinod Koul wrote:
> >>> On Tue, May 26, 2
On Thu, Jun 04, 2015 at 06:58:06PM +0300, Peter Ujfalusi wrote:
> Vinod,
>
> On 06/02/2015 03:55 PM, Vinod Koul wrote:
> > On Fri, May 29, 2015 at 05:32:50PM +0300, Peter Ujfalusi wrote:
> >> On 05/29/2015 01:18 PM, Vinod Koul wrote:
> >>> On Fri, May
On Mon, Jun 22, 2015 at 02:31:00PM +0300, Peter Ujfalusi wrote:
> On 06/12/2015 03:58 PM, Vinod Koul wrote:
> > Sorry this slipped thru
>
> I was away for a week anyways ;)
>
> > Thinking about it again, I think we should coverge to two APIs and mark the
> >
On Thu, Jul 30, 2015 at 05:41:05PM +0530, Rameshwar Prasad Sahu wrote:
> This patch adds support for new feature CRC32C calculation in
> dmaengine framework.
Looks okay can you please update Documentation also
--
~Vinod
--
To unsubscribe from this list: send the line "unsubscribe linux-crypto"
On Thu, Jul 30, 2015 at 05:41:06PM +0530, Rameshwar Prasad Sahu wrote:
> + /* Invalidate unused source address field */
> + for (; i < 4; i++)
> + xgene_dma_invalidate_buffer(xgene_dma_lookup_ext8(desc2, i));
> +
> + /* Check whether requested buffer processed */
> + if
On Thu, Jul 30, 2015 at 05:41:07PM +0530, Rameshwar Prasad Sahu wrote:
> + nents = sg_nents(req->src);
> + sg_count = dma_map_sg(dev, req->src, nents, DMA_TO_DEVICE);
> + if (!sg_count) {
> + dev_err(dev, "Failed to map src sg");
> + return -ENOMEM;
mapping error
On Thu, Aug 20, 2015 at 11:59:07AM +0530, Rameshwar Sahu wrote:
> Hi Vinod,
>
> On Thu, Aug 20, 2015 at 10:56 AM, Vinod Koul wrote:
> > On Thu, Jul 30, 2015 at 05:41:05PM +0530, Rameshwar Prasad Sahu wrote:
> >> This patch adds support for new feature CRC32C calcu
On Thu, Aug 20, 2015 at 12:23:50PM +0530, Rameshwar Sahu wrote:
> Hi Vinod,
>
> On Thu, Aug 20, 2015 at 11:10 AM, Vinod Koul wrote:
> > On Thu, Jul 30, 2015 at 05:41:06PM +0530, Rameshwar Prasad Sahu wrote:
> >> + /* Invalidate unused source address field */
&g
On Thu, Aug 20, 2015 at 12:31:44PM +0530, Rameshwar Sahu wrote:
> Hi Vinod,
>
> On Thu, Aug 20, 2015 at 11:18 AM, Vinod Koul wrote:
> > On Thu, Jul 30, 2015 at 05:41:07PM +0530, Rameshwar Prasad Sahu wrote:
> >> + nents = sg_nents(req->src);
> >> +
On Wed, Nov 18, 2015 at 04:51:54PM +0100, Arnd Bergmann wrote:
> On Wednesday 18 November 2015 17:43:04 Andy Shevchenko wrote:
> > >
> > > I assume that the sst-firmware.c case is a mistake, it should just use a
> > > plain DMA_SLAVE and not DMA_MEMCPY.
> >
> > Other way around.
> >
>
> Ok, I se
On Mon, Mar 06, 2017 at 03:13:24PM +0530, Anup Patel wrote:
> The Broadcom SBA RAID is a stream-based device which provides
> RAID5/6 offload.
>
> It requires a SoC specific ring manager (such as Broadcom FlexRM
> ring manager) to provide ring-based programming interface. Due to
> this, the Broadc
On Tue, Mar 21, 2017 at 02:17:21PM +0530, Anup Patel wrote:
> On Tue, Mar 21, 2017 at 2:00 PM, Vinod Koul wrote:
> > On Mon, Mar 06, 2017 at 03:13:24PM +0530, Anup Patel wrote:
> >> The Broadcom SBA RAID is a stream-based device which provides
> >> RAID5/6 offload.
On Wed, Mar 29, 2017 at 11:35:43AM +0530, Anup Patel wrote:
> On Tue, Mar 21, 2017 at 2:48 PM, Vinod Koul wrote:
> > On Tue, Mar 21, 2017 at 02:17:21PM +0530, Anup Patel wrote:
> >> On Tue, Mar 21, 2017 at 2:00 PM, Vinod Koul wrote:
> >> > On Mon, Mar 06, 2017 a
On Wed, May 03, 2017 at 09:15:20AM +0530, Anup Patel wrote:
> Hi Vinod,
>
> The Broadcom FlexRM patchset have been
> merged in v4.11.
>
> I think you now can take this patchset in next
> merge window. Right??
Sure, please rebase and resend after -rc1 is out
--
~Vinod
On Mon, May 15, 2017 at 10:34:51AM +0530, Anup Patel wrote:
> The Broadcom SBA RAID is a stream-based device which provides
> RAID5/6 offload.
>
> It requires a SoC specific ring manager (such as Broadcom FlexRM
> ring manager) to provide ring-based programming interface. Due to
> this, the Broadc
On Fri, Apr 26, 2013 at 10:28:39AM +0200, Linus Walleij wrote:
> On Thu, Apr 25, 2013 at 4:11 PM, Arnd Bergmann wrote:
>
> > The dma engine driver must know the address in its dma space, while the
> > slave driver has it available in physical space. These two are often the
> > same, but there is
On Fri, Apr 26, 2013 at 10:41:23AM +0100, Russell King - ARM Linux wrote:
> On Fri, Apr 26, 2013 at 01:46:46PM +0530, Vinod Koul wrote:
> > On Fri, Apr 26, 2013 at 10:28:39AM +0200, Linus Walleij wrote:
> > > On Thu, Apr 25, 2013 at 4:11 PM, Arnd Bergmann wrote:
> > &
e will need to be tailored. Fortunately, these platforms will be DT
> only, so this change has very little impact on platform data.
>
> Cc: Vinod Koul
> Cc: Dan Williams
> Cc: Per Forlin
> Cc: Rabin Vincent
> Acked-by: Arnd Bergmann
> Signed-off-by: Lee Jones
Acked
On Wed, May 15, 2013 at 10:51:56AM +0100, Lee Jones wrote:
> The aim is to make the code that little more readable.
>
> Cc: Vinod Koul
> Cc: Dan Williams
> Cc: Per Forlin
> Cc: Rabin Vincent
> Signed-off-by: Lee Jones
Acked-by: Vinod Koul
Hopefully all the BIT convers
On Wed, May 15, 2013 at 10:51:54AM +0100, Lee Jones wrote:
> STEDMA40_*_TO_* direction definitions are identical in all but name to
> the pre-defined generic DMA_*_TO_* ones. Let's make things easy by not
> duplicating such things.
>
> Cc: Vinod Koul
> Cc: Dan Williams
this (or check whom to blame)
--
~Vinod
>
> Cc: Vinod Koul
> Cc: Dan Williams
> Cc: Per Forlin
> Cc: Rabin Vincent
> Signed-off-by: Lee Jones
> ---
> drivers/dma/ste_dma40_ll.c |6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> d
ropriately, so we may as well add the infrastructure.
>
> Cc: Vinod Koul
> Cc: Dan Williams
> Cc: Per Forlin
> Cc: Rabin Vincent
> Acked-by: Arnd Bergmann
> Signed-off-by: Lee Jones
Acked-by: Vinod Koul
> ---
> Documentation/devicetree/bindings/dma/ste-dm
s we have to shift '1' by the bit pattern (1 << data_width)
> times to make any sense of it.
>
> This patch flips the semantics on its head and only converts the value
> to its respective register bit pattern when writing to registers. This
> way we can use the true
iately, so we may as well add the infrastructure.
>
> Cc: Vinod Koul
> Cc: Dan Williams
> Cc: Per Forlin
> Cc: Rabin Vincent
> Signed-off-by: Lee Jones
> ---
Acked-by: Vinod Koul
> drivers/dma/ste_dma40.c |7 ++-
> 1 file changed, 6 insertions(+), 1 deletio
t; > We're separating out this required code so it will be possible to move
> > the remaining code in d40_phy_cfg(), which is mostly runtime configuration
> > into the runtime_config() routine.
> >
> > Cc: Vinod Koul
> > Cc: Dan Williams
> > Cc: Per Forli
On Wed, May 15, 2013 at 10:51:25AM +0100, Lee Jones wrote:
> All configuration left in d40_phy_cfg() is runtime configurable and
> there is already a call into it from d40_runtime_config(), so let's
> rely on that.
>
> Acked-by: Vinod Koul
That needs up update!
>
On Wed, May 15, 2013 at 10:51:26AM +0100, Lee Jones wrote:
> Using the dmaengine API, allocating and configuring a channel are two
> separate actions. Here we're removing logical channel configuration from
> the channel allocating routines.
>
> Cc: Vinod Koul
> Cc: Dan Wil
On Wed, May 15, 2013 at 10:51:31AM +0100, Lee Jones wrote:
> Addresses are now stored in local data structures and are easy to
> obtain, thus a specialist function used to fetch them is now surplus
> to requirement.
>
> Signed-off-by: Lee Jones
> ---
Acked-by: Vinod Koul
--
> elevates a large burden from platform data in the way of a look-up
> table.
>
> Signed-off-by: Lee Jones
> ---
Good code size reduction, always a good template for code improvements
Acked-by: Vinod Koul
--
~Vinod
> drivers/dma/ste_dma40.c | 51
> ++---
On Wed, May 15, 2013 at 10:51:33AM +0100, Lee Jones wrote:
> 'struct stedma40_half_channel_info's header comment says that it's
> called 'struct stedma40_chan_cfg'. Let's straighten that out.
>
> Signed-off-by: Lee Jones
> ---
Acked-by: Vinod Koul
On Thu, May 16, 2013 at 08:06:38AM +0100, Lee Jones wrote:
> On Thu, 16 May 2013, Vinod Koul wrote:
>
> > On Wed, May 15, 2013 at 10:51:54AM +0100, Lee Jones wrote:
> > > STEDMA40_*_TO_* direction definitions are identical in all but name to
> > > the pre-defined
On Thu, May 16, 2013 at 08:25:57AM +0100, Lee Jones wrote:
> On Thu, 16 May 2013, Vinod Koul wrote:
>
> > On Wed, May 15, 2013 at 10:51:25AM +0100, Lee Jones wrote:
> > > All configuration left in d40_phy_cfg() is runtime configurable and
> > > there
On Thu, May 16, 2013 at 08:35:53AM +0100, Lee Jones wrote:
> On Thu, 16 May 2013, Vinod Koul wrote:
>
> > On Wed, May 15, 2013 at 10:51:57AM +0100, Lee Jones wrote:
> > > +u8 d40_width_to_bits(enum dma_slave_buswidth width)
> > > +{
> > > +
> of the statement OR:ing with 0.
> >
> > Cc: Vinod Koul
> > Cc: Dan Williams
> > Cc: Per Forlin
> > Cc: Rabin Vincent
> > Signed-off-by: Lee Jones
>
> Tentatively applied. Missing Vinod's ACK.
Acked-by: Vinod Koul
--
~Vinod
--
To unsu
On Thu, Sep 19, 2013 at 10:48:01PM +0100, Russell King wrote:
> The DMA API requires drivers to call the appropriate dma_set_mask()
> functions before doing any DMA mapping. Add this required call to
> the AMBA PL08x driver.
>
> Signed-off-by: Russell King
Acked-by: Vino
this driver.
>
> Signed-off-by: Russell King
Acked-by: Vinod Koul
This also brings me question that should we force the driver to use the
dma_set_mask_and_coherent() API or they have below flexiblity too?
~Vinod
> ---
> drivers/dma/edma.c |6 ++
> 1 files changed, 2
()
> > > functions before doing any DMA mapping. Add this required call to
> > > the AMBA PL08x driver.
> > ^--- copy and paste error - should of course be PL330
>
> Fixed, thanks.
with fixed changelog...
Acked-by: Vinod Koul
~Vinod
--
so add the necessary includes
> to fix ppc4xx builds.
>
> Signed-off-by: Rob Herring
> Cc: Benjamin Herrenschmidt
> Cc: Paul Mackerras
> Cc: Tejun Heo
> Cc: Matt Mackall
> Cc: Herbert Xu
> Cc: "David S. Miller"
> Cc: Vinod Koul
> Cc
On 12-09-19, 12:01, Tomer Maimon wrote:
> Add Nuvoton NPCM BMC Random Number Generator(RNG) driver.
Is this a true RNG or a psedo RNG, in case of latter it should be added
in drivers/crypto/. See crypto_register_rng()
>
> Signed-off-by: Tomer Maimon
> ---
> drivers/char/hw_random/Kconfig|
On 05-01-21, 15:02, Thomas Bogendoerfer wrote:
> Signed-off-by: Thomas Bogendoerfer
Applied after fixing subsystem name, thanks
--
~Vinod
On 07-01-21, 17:40, Thomas Bogendoerfer wrote:
> On Wed, Jan 06, 2021 at 11:10:38AM -0800, Joe Perches wrote:
> > On Tue, 2021-01-05 at 15:02 +0100, Thomas Bogendoerfer wrote:
> > > Signed-off-by: Thomas Bogendoerfer
> > []
> > > diff --git a/drivers/dma/txx9dmac.h b/drivers/dma/txx9dmac.h
> > []
| 3 +--
> drivers/dma/pl330.c| 3 +--
For dmaengine:
Acked-By: Vinod Koul
--
~Vinod
li
> Cc: Ray Jui
> Cc: Scott Branden
> Cc: Pavel Machek
> Cc: Ulf Hansson
> Cc: Kishon Vijay Abraham I
> Cc: Vinod Koul
> Cc: Geert Uytterhoeven
> Cc: Linus Walleij
> Cc: Daniel Lezcano
> Cc: linux-crypto@vger.kernel.org
> Cc: dri-de...@lists.freedesktop.org
Now that we are adding new driver for prng in crypto, move the
binding as well.
Signed-off-by: Vinod Koul
---
Documentation/devicetree/bindings/{rng => crypto}/qcom,prng.txt | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename Documentation/devicetree/bindings/{rng => crypto
Later qcom chips support v2 of the prng, which exposes an EE
(Execution Environment) for OS to use so add new compatible
qcom,prng-ee for this.
Signed-off-by: Vinod Koul
---
Documentation/devicetree/bindings/crypto/qcom,prng.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff
Qcom 8996 and later chips features multiple Execution Environments
(EE) and secure world is typically responsible for configuring the
prng.
Add driver data for qcom,prng as 0 and qcom,prng-ee as 1 and use
that to skip initialization routine.
Signed-off-by: Vinod Koul
---
drivers/crypto/qcom
This ports the Qcom prng from older hw_random driver.
No change of functionality and move from hw_random to crypto
APIs is done.
Reviewed-by: Linus Walleij
Signed-off-by: Vinod Koul
---
drivers/crypto/Kconfig| 11 +++
drivers/crypto/Makefile | 1 +
drivers/crypto/qcom-rng.c | 208
configure it.
Signed-off-by: Timur Tabi
Tested-by: Jeffrey Hugo
[port to crypto API]
Signed-off-by: Vinod Koul
---
drivers/crypto/qcom-rng.c | 20 +---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/qcom-rng.c b/drivers/crypto/qcom-rng.c
index
This driver is for a psedo-rng so should not be added in hwrng.
Remove it so that it's replacement can be added.
Signed-off-by: Vinod Koul
---
drivers/char/hw_random/Kconfig | 13 ---
drivers/char/hw_random/Makefile | 1 -
drivers/char/hw_random/msm-rng.c
tested tags
Changes in v5:
- Update ACPI check and use generic driver data API
Changes in v4:
- Use memcpy for data copy
- Fix trailing bytes copy
- Fix ACPI ID table name
Timur Tabi (1):
crypto: qcom: Add ACPI support
Vinod Koul (5):
hwrng: remove msm hw_random driver
dt-bindings
This driver is for a psedo-rng so should not be added in hwrng.
Remove it so that it's replacement can be added.
Signed-off-by: Vinod Koul
---
drivers/char/hw_random/Kconfig | 13 ---
drivers/char/hw_random/Makefile | 1 -
drivers/char/hw_random/msm-rng.c
configure it.
Signed-off-by: Timur Tabi
[port to crypto API]
Signed-off-by: Vinod Koul
---
drivers/crypto/qcom-rng.c | 37 +
1 file changed, 33 insertions(+), 4 deletions(-)
diff --git a/drivers/crypto/qcom-rng.c b/drivers/crypto/qcom-rng.c
index fdbbcac7bcb8
Qcom 8996 and later chips features multiple Execution Environments
(EE) and secure world is typically responsible for configuring the
prng.
Add driver data for qcom,prng as 0 and qcom,prng-ee as 1 and use
that to skip initialization routine.
Signed-off-by: Vinod Koul
---
drivers/crypto/qcom
This series removes the hwrng qcom driver and replaces it with crypto qcom
driver and then adds support for Execution Environment (EE) found in v2
version of the hardware and ACPI support for these
Timur Tabi (1):
crypto: qcom: Add ACPI support
Vinod Koul (5):
hwrng: remove msm hw_random
Later qcom chips support v2 of the prng, which exposes an EE
(Execution Enviornment) for OS to use so add new compatible
qcom,prng-ee for this.
Signed-off-by: Vinod Koul
---
Documentation/devicetree/bindings/crypto/qcom,prng.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff
This ports the Qcom prng from older hw_random driver.
No change of functionality and move from hw_random to crypto
APIs is done.
Signed-off-by: Vinod Koul
---
drivers/crypto/Kconfig| 11 +++
drivers/crypto/Makefile | 1 +
drivers/crypto/qcom-rng.c | 208
Now that we are adding new driver for prng in crypto, move the
binding as well.
Signed-off-by: Vinod Koul
---
Documentation/devicetree/bindings/{rng => crypto}/qcom,prng.txt | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename Documentation/devicetree/bindings/{rng => crypto
Qcom 8996 and later chips features multiple Execution Environments
(EE) and secure world is typically responsible for configuring the
prng.
Add driver data for qcom,prng as 0 and qcom,prng-ee as 1 and use
that to skip initialization routine.
Signed-off-by: Vinod Koul
---
drivers/crypto/qcom
configure it.
Signed-off-by: Timur Tabi
[port to crypto API]
Signed-off-by: Vinod Koul
---
drivers/crypto/qcom-rng.c | 30 ++
1 file changed, 26 insertions(+), 4 deletions(-)
diff --git a/drivers/crypto/qcom-rng.c b/drivers/crypto/qcom-rng.c
index f1bd86acaf9d..385352e200db
This ports the Qcom prng from older hw_random driver.
No change of functionality and move from hw_random to crypto
APIs is done.
Signed-off-by: Vinod Koul
---
drivers/crypto/Kconfig| 11 +++
drivers/crypto/Makefile | 1 +
drivers/crypto/qcom-rng.c | 208
Later qcom chips support v2 of the prng, which exposes an EE
(Execution Environment) for OS to use so add new compatible
qcom,prng-ee for this.
Signed-off-by: Vinod Koul
---
Documentation/devicetree/bindings/crypto/qcom,prng.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff
Timur Tabi (1):
crypto: qcom: Add ACPI support
Vinod Koul (5):
hwrng: remove msm hw_random driver
dt-bindings: crypto: Move prng binding to crypto
crypto: Add Qcom prng driver
dt-bindings: crypto: Add new compatible qcom,prng-ee
crypto: qcom: Add support for prng-ee
.../bindings/{rng
Now that we are adding new driver for prng in crypto, move the
binding as well.
Signed-off-by: Vinod Koul
---
Documentation/devicetree/bindings/{rng => crypto}/qcom,prng.txt | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename Documentation/devicetree/bindings/{rng => crypto
This driver is for a pseudo-rng so should not be added in hwrng.
Remove it so that it's replacement can be added.
Signed-off-by: Vinod Koul
---
drivers/char/hw_random/Kconfig | 13 ---
drivers/char/hw_random/Makefile | 1 -
drivers/char/hw_random/msm-rng.c
This driver is for a psedo-rng so should not be added in hwrng.
Remove it so that it's replacement can be added.
Signed-off-by: Vinod Koul
---
drivers/char/hw_random/Kconfig | 13 ---
drivers/char/hw_random/Makefile | 1 -
drivers/char/hw_random/msm-rng.c
for data copy
- Fix trailing bytes copy
- Fix ACPI ID table name
Timur Tabi (1):
crypto: qcom: Add ACPI support
Vinod Koul (5):
hwrng: remove msm hw_random driver
dt-bindings: crypto: Move prng binding to crypto
crypto: Add Qcom prng driver
dt-bindings: crypto: Add new compatible qcom
Later qcom chips support v2 of the prng, which exposes an EE
(Execution Environment) for OS to use so add new compatible
qcom,prng-ee for this.
Signed-off-by: Vinod Koul
---
Documentation/devicetree/bindings/crypto/qcom,prng.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff
This ports the Qcom prng from older hw_random driver.
No change of functionality and move from hw_random to crypto
APIs is done.
Signed-off-by: Vinod Koul
---
drivers/crypto/Kconfig| 11 +++
drivers/crypto/Makefile | 1 +
drivers/crypto/qcom-rng.c | 208
Qcom 8996 and later chips features multiple Execution Environments
(EE) and secure world is typically responsible for configuring the
prng.
Add driver data for qcom,prng as 0 and qcom,prng-ee as 1 and use
that to skip initialization routine.
Signed-off-by: Vinod Koul
---
drivers/crypto/qcom
configure it.
Signed-off-by: Timur Tabi
[port to crypto API]
Signed-off-by: Vinod Koul
---
drivers/crypto/qcom-rng.c | 22 ++
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/crypto/qcom-rng.c b/drivers/crypto/qcom-rng.c
index f1bd86acaf9d..8118d4cd93b2 100644
Now that we are adding new driver for prng in crypto, move the
binding as well.
Signed-off-by: Vinod Koul
---
Documentation/devicetree/bindings/{rng => crypto}/qcom,prng.txt | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename Documentation/devicetree/bindings/{rng => crypto
84 matches
Mail list logo
