On Thu, 2020-09-17 at 18:58 +0530, Srujana Challa wrote:
> The following series adds support for Marvell Cryptographic
> Acceleration
> Unit(CPT) on OcteonTX2 CN96XX SoC.
> This series is tested with CRYPTO_EXTRA_TESTS enabled and
> CRYPTO_DISABLE_TESTS disabled.
>
I am with Jakub on this one, 10
On Thu, 2020-09-17 at 18:58 +0530, Srujana Challa wrote:
>
>
> +int rvu_mbox_handler_nix_inline_ipsec_lf_cfg(struct rvu *rvu,
>
> + struct nix_inline_ipsec_lf_cfg *req, struct msg_rsp
>
Can you do something about this code alignment ?
checkpatch outputs:
--
On Thu, 2020-09-17 at 18:58 +0530, Srujana Challa wrote:
> Add support for the cryptographic acceleration unit (CPT) on
>
> OcteonTX2 CN96XX SoC.
>
>
>
> Signed-off-by: Suheil Chandran
>
> Signed-off-by: Lukas Bartosik
>
> Signed-off-by: Srujana Challa
>
> ---
[...]
> 15 files changed,
rgument passed by the
> > caller,
> > which usually knows the context.
> >
> > mlx5_eq_async_int() knows the context via the action argument
> > already so
> > using it for the lock variant decision is a straight forward
> > replacement
> > for in_irq().
> &g
rgument passed by the
> > caller,
> > which usually knows the context.
> >
> > mlx5_eq_async_int() knows the context via the action argument
> > already so
> > using it for the lock variant decision is a straight forward
> > replacement
> > for in_irq().
> &g