)
- sha256 and hmac(sha256)
- sha384 and hmac(sha384)
- sha512 and hmac(sha512)
- sm3and hmac(sm3)
The driver is passing crypto manager self-tests, including the extra tests
(CRYPTO_MANAGER_EXTRA_TESTS=y).
Daniele Alessandrelli (1):
MAINTAINERS: Add maintainers for Keem Bay OCS HCU driver
From: Daniele Alessandrelli
Add maintainers for the Intel Keem Bay Offload Crypto Subsystem (OCS)
Hash Control Unit (HCU) crypto driver.
Signed-off-by: Daniele Alessandrelli
---
MAINTAINERS | 11 +++
1 file changed, 11 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index
and hmac(sha384)
- sha512 and hmac(sha512)
- sm3and hmac(sm3)
The driver passes crypto manager self-tests, including the extra tests
(CRYPTO_MANAGER_EXTRA_TESTS=y).
Signed-off-by: Declan Murphy
Co-developed-by: Daniele Alessandrelli
Signed-off-by: Daniele Alessandrelli
Acked-by: Mark Gross
From: Declan Murphy
Add device-tree bindings for the Intel Keem Bay Offload Crypto Subsystem
(OCS) Hashing Control Unit (HCU) crypto driver.
Signed-off-by: Declan Murphy
Signed-off-by: Daniele Alessandrelli
Acked-by: Mark Gross
---
.../crypto/intel,keembay-ocs-hcu.yaml | 52
Hi Rob,
Thanks for reviewing the patch.
On Mon, 2020-10-26 at 08:17 -0500, Rob Herring wrote:
> On Fri, Oct 16, 2020 at 06:27:57PM +0100, Daniele Alessandrelli
> wrote:
> > From: Declan Murphy
> >
> > Add device-tree bindings for the Intel Keem Bay Offload Crypt
and hmac(sha384)
- sha512 and hmac(sha512)
- sm3and hmac(sm3)
The driver passes crypto manager self-tests, including the extra tests
(CRYPTO_MANAGER_EXTRA_TESTS=y).
Signed-off-by: Declan Murphy
Co-developed-by: Daniele Alessandrelli
Signed-off-by: Daniele Alessandrelli
Acked-by: Mark Gross
)
- sha256 and hmac(sha256)
- sha384 and hmac(sha384)
- sha512 and hmac(sha512)
- sm3and hmac(sm3)
The driver is passing crypto manager self-tests, including the extra tests
(CRYPTO_MANAGER_EXTRA_TESTS=y).
v1 -> v2:
- Fixed issues with dt-bindings
Daniele Alessandrelli (1):
MAINTAINERS:
From: Daniele Alessandrelli
Add maintainers for the Intel Keem Bay Offload Crypto Subsystem (OCS)
Hash Control Unit (HCU) crypto driver.
Signed-off-by: Daniele Alessandrelli
---
MAINTAINERS | 11 +++
1 file changed, 11 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index
From: Declan Murphy
Add device-tree bindings for the Intel Keem Bay Offload Crypto Subsystem
(OCS) Hashing Control Unit (HCU) crypto driver.
Signed-off-by: Declan Murphy
Signed-off-by: Daniele Alessandrelli
Acked-by: Mark Gross
---
.../crypto/intel,keembay-ocs-hcu.yaml | 51
On Mon, 2020-11-09 at 10:15 -0600, Rob Herring wrote:
> On Tue, Nov 03, 2020 at 06:49:23PM +0000, Daniele Alessandrelli wrote:
> > From: Declan Murphy
> >
> > Add device-tree bindings for the Intel Keem Bay Offload Crypto Subsystem
> > (OCS) Hashing Contr
reg,
interrupts, and clocks)
v1 -> v2:
- Fixed issues with dt-bindings
Daniele Alessandrelli (1):
MAINTAINERS: Add maintainers for Keem Bay OCS HCU driver
Declan Murphy (2):
dt-bindings: crypto: Add Keem Bay OCS HCU bindings
crypto: keembay: Add Keem Bay OCS HCU driver
.../crypto/intel,k
and hmac(sha384)
- sha512 and hmac(sha512)
- sm3and hmac(sm3)
The driver passes crypto manager self-tests, including the extra tests
(CRYPTO_MANAGER_EXTRA_TESTS=y).
Signed-off-by: Declan Murphy
Co-developed-by: Daniele Alessandrelli
Signed-off-by: Daniele Alessandrelli
Acked-by: Mark Gross
From: Daniele Alessandrelli
Add maintainers for the Intel Keem Bay Offload Crypto Subsystem (OCS)
Hash Control Unit (HCU) crypto driver.
Signed-off-by: Daniele Alessandrelli
Acked-by: Declan Murphy
---
MAINTAINERS | 11 +++
1 file changed, 11 insertions(+)
diff --git a/MAINTAINERS b
From: Declan Murphy
Add device-tree bindings for the Intel Keem Bay Offload Crypto Subsystem
(OCS) Hashing Control Unit (HCU) crypto driver.
Signed-off-by: Declan Murphy
Signed-off-by: Daniele Alessandrelli
Acked-by: Mark Gross
---
.../crypto/intel,keembay-ocs-hcu.yaml | 46
driver is different from the Keem Bay OCS HCU driver previously
submitted. Keem Bay OCS HCU provides hardware-accelerated ahash, while
Keem Bay AES/SM4 (i.e., this driver) provides hardware-accelerated
skcipher and aead.
Daniele Alessandrelli (1):
dt-bindings: Add Keem Bay OCS AES bindings
Mike
From: Daniele Alessandrelli
Add device-tree bindings for Intel Keem Bay Offload and Crypto Subsystem
(OCS) AES crypto driver.
Signed-off-by: Daniele Alessandrelli
Acked-by: Mark Gross
---
.../crypto/intel,keembay-ocs-aes.yaml | 45 +++
1 file changed, 45 insertions
128-bit and 256-bit keys.
- ecb(sm4), cbc(sm4), ctr(sm4), cts(cbc(sm4)), gcm(sm4) and cbc(sm4);
supported for 128-bit keys.
The driver passes crypto manager self-tests, including the extra tests
(CRYPTO_MANAGER_EXTRA_TESTS=y).
Signed-off-by: Mike Healy
Co-developed-by: Daniele Alessandrelli
yourself in each case : "what can an admin do with the output or is it
> actionable?"
In v4 (soon to be submitted), I've tried to improve error messages.
>
>
> On Mon, Nov 16, 2020 at 06:58:45PM +, Daniele Alessandrelli wrote:
> > From: Declan Murphy
&g
From: Declan Murphy
Add device-tree bindings for the Intel Keem Bay Offload Crypto Subsystem
(OCS) Hashing Control Unit (HCU) crypto driver.
Signed-off-by: Declan Murphy
Signed-off-by: Daniele Alessandrelli
Acked-by: Mark Gross
Reviewed-by: Rob Herring
---
.../crypto/intel,keembay-ocs
ith dt-bindings (removed useless descriptions for reg,
interrupts, and clocks)
v1 -> v2:
- Fixed issues with dt-bindings
Daniele Alessandrelli (3):
crypto: keembay-ocs-hcu - Add HMAC support
crypto: keembay-ocs-hcu - Add optional support for sha224
MAINTAINERS: Add maintainers for Keem Ba
apping of the input sg list.
The driver passes crypto manager self-tests, including the extra tests
(CRYPTO_MANAGER_EXTRA_TESTS=y).
Signed-off-by: Declan Murphy
Co-developed-by: Daniele Alessandrelli
Signed-off-by: Daniele Alessandrelli
Acked-by: Mark Gross
---
drivers/crypto/keembay/Kconfi
From: Daniele Alessandrelli
Add HMAC support to the Keem Bay OCS HCU driver, thus making it provide
the following additional transformations:
- hmac(sha256)
- hmac(sha384)
- hmac(sha512)
- hmac(sm3)
The Keem Bay OCS HCU hardware does not allow "context-switch" for HMAC
operations, i.e
From: Daniele Alessandrelli
Add optional support of sha224 and hmac(sha224).
Co-developed-by: Declan Murphy
Signed-off-by: Declan Murphy
Signed-off-by: Daniele Alessandrelli
---
drivers/crypto/keembay/Kconfig| 12
drivers/crypto/keembay/keembay-ocs-hcu-core.c | 63
From: Daniele Alessandrelli
Add maintainers for the Intel Keem Bay Offload Crypto Subsystem (OCS)
Hash Control Unit (HCU) crypto driver.
Signed-off-by: Daniele Alessandrelli
Acked-by: Declan Murphy
---
MAINTAINERS | 11 +++
1 file changed, 11 insertions(+)
diff --git a/MAINTAINERS b
From: Daniele Alessandrelli
Add dependency for CRYPTO_DEV_KEEMBAY_OCS_AES_SM4 on HAS_IOMEM to
prevent build failures.
Fixes: 88574332451380f4 ("crypto: keembay - Add support for Keem Bay OCS
AES/SM4")
Reported-by: kernel test robot
Signed-off-by: Daniele Alessandrelli
---
driv
From: Daniele Alessandrelli
Move ecc.h header file to 'include/crypto/internal' so that it can be
easily imported from everywhere in the kernel tree.
This change is done to allow crypto device drivers to re-use the symbols
exported by 'crypto/ecc.c', thus avoiding code dupl
ver passes the P-256 self test only when
CONFIG_CRYPTO_DEV_KEEMBAY_OCS_ECDH_GEN_PRIV_KEY_SUPPORT=y. Is that
acceptable?
Daniele Alessandrelli (2):
crypto: ecc - Move ecc.h to include/crypto/internal
crypto: ecc - Export additional helper functions
Prabhjot Khurana (4):
crypto: engine - Add KPP Support to Crypto Engine
crypto:
From: Prabhjot Khurana
Reserve ECC curve id for NIST P-384 curve.
This is done to prepare for future support of the P-384 curve by KPP
device drivers.
Signed-off-by: Prabhjot Khurana
Signed-off-by: Daniele Alessandrelli
---
include/crypto/ecdh.h | 1 +
1 file changed, 1 insertion(+)
diff
From: Daniele Alessandrelli
Export the following additional ECC helper functions:
- ecc_alloc_point()
- ecc_free_point()
- vli_num_bits()
- ecc_point_is_zero()
- ecc_swap_digits()
This is done to allow future KPP device drivers to re-use existing code,
thus simplifying their implementation
From: Prabhjot Khurana
Add Keem Bay Offload and Crypto Subsystem (OCS) Elliptic Curve
Cryptography (ECC) device tree bindings.
Signed-off-by: Prabhjot Khurana
Signed-off-by: Daniele Alessandrelli
---
.../crypto/intel,keembay-ocs-ecc.yaml | 47 +++
MAINTAINERS
From: Prabhjot Khurana
Add KPP support to the crypto engine queue manager, so that it can be
used to simplify the logic of KPP device drivers as done for other
crypto drivers.
Signed-off-by: Prabhjot Khurana
Signed-off-by: Daniele Alessandrelli
---
Documentation/crypto/crypto_engine.rst | 4
ECDH-384.
Signed-off-by: Prabhjot Khurana
Co-developed-by: Daniele Alessandrelli
Signed-off-by: Daniele Alessandrelli
---
MAINTAINERS |4 +
drivers/crypto/keembay/Kconfig | 31 +
drivers/crypto/keembay/Makefile |2 +
drivers
From: Daniele Alessandrelli
Add the following additional dependencies for CRYPTO_DEV_KEEMBAY_OCS_HCU:
- HAS_IOMEM to prevent build failures
- ARCH_KEEMBAY to prevent asking the user about this driver when
configuring a kernel without Intel Keem Bay platform support.
Signed-off-by: Daniele
On Thu, 2021-01-28 at 21:39 +1100, Herbert Xu wrote:
> Once they're distinct algorithms, we can then make sure that only
> the ones that are used in the kernel is added, even if some hardware
> may support more curves.
I like the idea of having different algorithms names (ecdh-nist-
pXXX) for diff
From: Daniele Alessandrelli
The length ('len' parameter) passed to crypto_ecdh_decode_key() is never
checked against the length encoded in the passed buffer ('buf'
parameter). This could lead to an out-of-bounds access when the passed
length is less than the encoded len
From: Daniele Alessandrelli
In ocs_aes_ccm_write_b0(), 'q' (the octet length of the binary
representation of the octet length of the payload) is set to 'iv[0]',
while it should be set to 'iv[0] & 0x7' (i.e., only the last 3
bits of iv[0] should be used), as docu
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