This patch series enables VAS / NX-GZIP on powerVM which allows
the user space to do copy/paste with the same existing interface
that is available on powerNV.
VAS Enablement:
- Get all VAS capabilities using H_QUERY_VAS_CAPABILITIES that are
available in the hypervisor. These capabilities tell
powerNV and pseries drivers register / unregister to the corresponding
VAS code separately. So rename powerNV VAS API register/unregister
functions.
Signed-off-by: Haren Myneni
---
arch/powerpc/include/asm/vas.h | 6 +++---
arch/powerpc/platforms/powernv/vas-api.c | 10 +-
d
Using the same /dev/crypto/nx-gzip interface for both powerNV and
pseries. So this patch moves VAS API to powerpc platform indepedent
directory. The actual functionality is not changed in this patch.
Common interface functions such as open, window open ioctl, mmap
and close are moved to arch/pow
Take task reference when each window opens and drops during close.
This functionality is needed for powerNV and pseries. So this patch
defines the existing code as functions in powerpc platform
independent vas-api.c
Signed-off-by: Haren Myneni
---
arch/powerpc/include/asm/vas.h |
Same vas_window struct is used on powerNV and pseries. So this patch
changes in struct vas_window to support both platforms and also the
corresponding modifications in powerNV vas code.
On powerNV vas_window is used for both TX and RX windows, whereas
only for TX windows on powerVM. So some elem
This patch adds HCALLs and other definitions. Also define structs
that are used in VAS implementation on powerVM.
Signed-off-by: Haren Myneni
---
arch/powerpc/include/asm/hvcall.h| 7 ++
arch/powerpc/include/asm/vas.h | 28
arch/powerpc/platforms/pseries/vas.h | 96
NX issues an interrupt when sees fault on user space buffer. The
kernel processes the fault by updating CSB. This functionality is
same for both powerNV and pseries. So this patch moves these
functions to vas-api.c and the actual functionality is not changed.
Signed-off-by: Haren Myneni
---
ar
pHyp introduces two different type of credits: Default and Quality
of service (QoS).
The total number of default credits available on each LPAR depends
on CPU resources configured. But these credits can be shared or
over-committed across LPARs in shared mode which can result in
paste command fai
When NX sees a fault on the user space buffer, generates a fault
interrupt and pHyp forwards that interrupt to OS. Then the kernel
makes H_GET_NX_FAULT HCALL to retrieve the fault CRB information.
This patch adds changes to setup IRQ per each window and handles
fault by updating CSB.
Signed-off
This patch adds the following HCALLs which are used to allocate,
modify and deallocate VAS windows.
H_ALLOCATE_VAS_WINDOW: Allocate VAS window
H_DEALLOCATE_VAS_WINDOW: Close VAS window
H_MODIFY_VAS_WINDOW: Setup window before using
Also adds phyp call (H_QUERY_VAS_CAPABILITIES) to get all VAS
c
pHyp provides various VAS capabilities such as GZIP default and QoS
capabilities which are used to determine total number of credits
available in LPAR, maximum window credits, maximum LPAR credits,
whether usermode copy/paste is supported, and etc.
So first retrieve overall vas capabilities usin
pHyp provides GZIP default and GZIP QoS capabilities which gives
the total number of credits are available in LPAR. This patch
creates sysfs entries and exports LPAR credits, the currently used
and the available credits for each feature.
/sys/kernel/vas/VasCaps/VDefGzip: (default GZIP capabiliti
This patch adds VAS window allocatioa/close with the corresponding
HCALLs. Also changes to integrate with the existing user space VAS
API and provide register/unregister functions to NX pseries driver.
The driver register function is used to create the user space
interface (/dev/crypto/nx-gzip)
Changes to create /dev/crypto/nx-gzip interface with VAS register
and to remove this interface with VAS unregister.
Signed-off-by: Haren Myneni
---
drivers/crypto/nx/Kconfig | 1 +
drivers/crypto/nx/nx-common-pseries.c | 9 +
2 files changed, 10 insertions(+)
diff --git a/
Rename nx-842-pseries.c to nx-common-pseries.c to add code for new
GZIP compression type. The actual functionality is not changed in
this patch.
Signed-off-by: Haren Myneni
---
drivers/crypto/nx/Makefile | 2 +-
drivers/crypto/nx/{nx-842-pseries.c => nx-common-
phyp provides NX capabilities which gives recommended minimum
compression / decompression length and maximum request buffer size
in bytes.
Changes to get NX overall capabilities which points to the specific
features phyp supports. Then retrieve NXGZIP specific capabilities.
Signed-off-by: Haren
Changes to export the following NXGZIP capabilities through sysfs:
/sys/devices/vio/ibm,compression-v1/NxGzCaps:
min_compress_len /*Recommended minimum compress length in bytes*/
min_decompress_len /*Recommended minimum decompress length in bytes*/
req_max_processed_len /* Maximum number of byt
From: Chris von Recklinghausen
> Sent: 12 April 2021 20:51
...
> > This is not about BIOS bugs. Hibernation is deep suspend/resume
> > grafted onto cold boot, and it is perfectly legal for the firmware to
> > present a different memory map to the OS after a cold boot. It is
> > Linux that decides t
From: Vaibhav Gupta
This patch series aims to modify necessary files before an entry for sa2ul
can be made in the respective am64 device tree.
v2?
- Simplify the dt-binding changes.
Peter Ujfalusi (3):
dt-bindings: crypto: ti,sa2ul: Add new compatible for AM64
crypto: sa2ul: Support for p
From: Peter Ujfalusi
Add the AM64 version of sa2ul to the compatible list.
[v_gu...@ti.com: Conditional dma-coherent requirement, clocks]
Signed-off-by: Peter Ujfalusi
Signed-off-by: Vaibhav Gupta
---
.../devicetree/bindings/crypto/ti,sa2ul.yaml | 24 ++-
1 file changed, 23 i
From: Peter Ujfalusi
The sa2ul module in am64 have limited support for algorithms, and the
priv and priv_id used on the platform is different compared to AM654 or
j721e.
Use match data to get the SoC specific information and use it throughout
the driver.
Signed-off-by: Peter Ujfalusi
Signed-of
From: Peter Ujfalusi
On AM64 the DMA channel for sa2ul can be configured to be coherent or
non coherent via DT binding.
Use the dmaengine_get_device_for_dma_api() to get the device pointer which
should be used for with the dma_api to use matching dma_ops for the
channel coherency/non coherency.
Christophe Leroy writes:
> Le 11/04/2021 à 02:31, Haren Myneni a écrit :
>>
>> Using the same /dev/crypto/nx-gzip interface for both powerNV and
>> pseries. So this patcb moves VAS API to powerpc platform indepedent
>> directory. The actual functionality is not changed in this patch.
>
> This pat
Hi,
On 3/9/21 10:10 AM, Lee, Chun-Yi wrote:
> This patch adds the logic for parsing the CodeSign extended key usage
> extension in X.509. The parsing result will be set to the eku flag
> which is carried by public key. It can be used in the PKCS#7
> verification.
>
> Signed-off-by: "Lee, Chun-Yi"
Suspend fails on a system in fips mode because md5 is used for the e820
integrity check and is not available. Use crc32 instead.
This patch changes the integrity check algorithm from md5 to crc32.
The check is intended to detect whether the E820 memory map provided
by the firmware after cold boot
On Tue, 13 Apr 2021 14:45:57 +0530, Vaibhav Gupta wrote:
> From: Peter Ujfalusi
>
> Add the AM64 version of sa2ul to the compatible list.
>
> [v_gu...@ti.com: Conditional dma-coherent requirement, clocks]
> Signed-off-by: Peter Ujfalusi
> Signed-off-by: Vaibhav Gupta
> ---
> .../devicetree/bi
Hi Bjorn,
Thanks for the reviews.
I realized that I had these replies in my draft for a while and forgot
to send them!
On 4/5/21 1:36 PM, Bjorn Andersson wrote:
On Thu 25 Feb 12:27 CST 2021, Thara Gopinath wrote:
MAC_FAILED gets set in the status register if authenthication fails
for ccm al
On 4/5/21 6:32 PM, Bjorn Andersson wrote:
On Thu 25 Feb 12:27 CST 2021, Thara Gopinath wrote:
rf4309 is the specification that uses aes ccm algorithms with IPsec
security packets. Add a submode to identify rfc4309 ccm(aes) algorithm
in the crypto driver.
Signed-off-by: Thara Gopinath
---
On Tue, Apr 13, 2021 at 12:13:30PM -0400, Chris von Recklinghausen wrote:
> +static inline void get_e820_crc32(struct e820_table *table, void *buf)
> {
This should just return the CRC-32 value as a u32. There's no need for the
'void *buf' argument.
Also like I said, compute_e820_crc32() would b
On Tue, Apr 13, 2021 at 12:13:30PM -0400, Chris von Recklinghausen wrote:
> Suspend fails on a system in fips mode because md5 is used for the e820
Suspend to disk (hibernation), or any suspend?
> struct restore_data_record {
> unsigned long jump_address;
> unsigned long jump_address
On Tue 13 Apr 14:30 CDT 2021, Thara Gopinath wrote:
>
>
> On 4/5/21 6:32 PM, Bjorn Andersson wrote:
> > On Thu 25 Feb 12:27 CST 2021, Thara Gopinath wrote:
> >
> > > rf4309 is the specification that uses aes ccm algorithms with IPsec
> > > security packets. Add a submode to identify rfc4309 ccm
Hi Bjorn,
On 4/5/21 6:18 PM, Bjorn Andersson wrote:
On Thu 25 Feb 12:27 CST 2021, Thara Gopinath wrote:
Add register programming sequence for enabling AEAD
algorithms on the Qualcomm crypto engine.
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/common.c | 155 ++
On Tue 13 Apr 16:31 CDT 2021, Thara Gopinath wrote:
>
> Hi Bjorn,
>
> On 4/5/21 6:18 PM, Bjorn Andersson wrote:
> > On Thu 25 Feb 12:27 CST 2021, Thara Gopinath wrote:
> >
> > > Add register programming sequence for enabling AEAD
> > > algorithms on the Qualcomm crypto engine.
> > >
> > > Sign
On 4/5/21 6:18 PM, Bjorn Andersson wrote:
On Thu 25 Feb 12:27 CST 2021, Thara Gopinath wrote:
Add register programming sequence for enabling AEAD
algorithms on the Qualcomm crypto engine.
Signed-off-by: Thara Gopinath
---
drivers/crypto/qce/common.c | 155
On Tue 13 Apr 17:27 CDT 2021, Thara Gopinath wrote:
>
>
> On 4/5/21 6:18 PM, Bjorn Andersson wrote:
> > On Thu 25 Feb 12:27 CST 2021, Thara Gopinath wrote:
> >
> > > Add register programming sequence for enabling AEAD
> > > algorithms on the Qualcomm crypto engine.
> > >
> > > Signed-off-by: T
On 4/13/21 6:20 PM, Bjorn Andersson wrote:
On Tue 13 Apr 16:31 CDT 2021, Thara Gopinath wrote:
Hi Bjorn,
On 4/5/21 6:18 PM, Bjorn Andersson wrote:
On Thu 25 Feb 12:27 CST 2021, Thara Gopinath wrote:
Add register programming sequence for enabling AEAD
algorithms on the Qualcomm crypto en
On 4/13/21 6:33 PM, Bjorn Andersson wrote:
On Tue 13 Apr 17:27 CDT 2021, Thara Gopinath wrote:
On 4/5/21 6:18 PM, Bjorn Andersson wrote:
On Thu 25 Feb 12:27 CST 2021, Thara Gopinath wrote:
Add register programming sequence for enabling AEAD
algorithms on the Qualcomm crypto engine.
Sig
On Tue 13 Apr 17:44 CDT 2021, Thara Gopinath wrote:
>
>
> On 4/13/21 6:20 PM, Bjorn Andersson wrote:
> > On Tue 13 Apr 16:31 CDT 2021, Thara Gopinath wrote:
> >
> > >
> > > Hi Bjorn,
> > >
> > > On 4/5/21 6:18 PM, Bjorn Andersson wrote:
> > > > On Thu 25 Feb 12:27 CST 2021, Thara Gopinath wro
Fix the following clang warning:
drivers/crypto/chelsio/chcr_algo.c:129:19: warning: unused function
'is_ofld_imm' [-Wunused-function].
Reported-by: Abaci Robot
Signed-off-by: Jiapeng Chong
---
drivers/crypto/chelsio/chcr_algo.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/c
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