Ben reports that CCM using AES-NI instructions performs pathologically
poorly, which is due to the overhead of preserving/restoring the SIMD
state, which is repeated after every 16 bytes of input when executing
the CBCMAC portion of the algorithm.
So let's clone the arm64 implementation of cbcmac(
> > Subject: [RESEND PATCH v5] mm/zswap: move to use crypto_acomp API for
> > hardware acceleration
> >
> > Right now, all new ZIP drivers are adapted to crypto_acomp APIs rather than
> > legacy crypto_comp APIs. Tradiontal ZIP drivers like lz4,lzo etc have been
> > also
> > wrapped into acomp via
In case of memory allocation failure, a negative error code should
be returned.
Fixes: 785e5c616c849 ("crypto: mediatek - Add crypto driver support for some
MediaTek chips")
Cc: Ryder Lee
Signed-off-by: Tianjia Zhang
---
drivers/crypto/mediatek/mtk-platform.c | 4 ++--
1 file changed, 2 insert
In qat_alg_sgl_to_bufl(), "bufl" and "buflout" are mapped to streaming DMA:
blp = dma_map_single(dev, bufl, sz, DMA_TO_DEVICE);
bloutp = dma_map_single(dev, buflout, sz_out, DMA_TO_DEVICE);
Then "bufl" and "buflout" are accessed at some places, such as:
bufl->bufers[y].len = sg->length;
b
In qm_qp_ctx_cfg(), "sqc" and "aeqc" are mapped to streaming DMA:
eqc_dma = dma_map_single(..., eqc, ...);
..
aeqc_dma = dma_map_single(..., aeqc, ...);
Then "sqc" and "aeqc" are accessed at many places, such as:
eqc->base_l = cpu_to_le32(lower_32_bits(qm->eqe_dma));
eqc->base_h = c
On 8/1/20 5:56 AM, Borislav Petkov wrote:
> On Sat, Aug 01, 2020 at 01:24:29PM +0200, Saheed O. Bolarinwa wrote:
>> The return value of pci_read_config_*() may not indicate a device error.
>> However, the value read by these functions is more likely to indicate
>> this kind of error. This present
Update the size used in 'dma_free_coherent()' in order to match the one
used in the corresponding 'dma_alloc_coherent()', in 'setup_crypt_desc()'.
Fixes: 81bef0150074 ("crypto: ixp4xx - Hardware crypto support for IXP4xx CPUs")
Signed-off-by: Christophe JAILLET
---
drivers/crypto/ixp4xx_crypto.c
From: Tom Rix
Clang static analysis reports this error
crypto/drbg.c:441:40: warning: Division by zero
padlen = (inputlen + sizeof(L_N) + 1) % (drbg_blocklen(drbg));
~^~~
When drbg_bocklen fails it returns 0.
if (
On 8/1/20 2:56 PM, Borislav Petkov wrote:
On Sat, Aug 01, 2020 at 01:24:29PM +0200, Saheed O. Bolarinwa wrote:
The return value of pci_read_config_*() may not indicate a device error.
However, the value read by these functions is more likely to indicate
this kind of error. This presents two ov
Am Sonntag, 2. August 2020, 19:12:47 CEST schrieb t...@redhat.com:
Hi Tom,
> From: Tom Rix
>
> Clang static analysis reports this error
>
> crypto/drbg.c:441:40: warning: Division by zero
> padlen = (inputlen + sizeof(L_N) + 1) % (drbg_blocklen(drbg));
> ~~
On Sun, Aug 02, 2020 at 07:28:00PM +0200, Saheed Bolarinwa wrote:
> Because the value ~0 has a meaning to some drivers and only
No, ~0 means that the PCI read failed. For *every* PCI device I know.
Here's me reading from 0xf0 offset of my hostbridge:
# setpci -s 00:00.0 0xf0.l
0100
That dev
On Sun, Aug 02, 2020 at 08:46:48PM +0200, Borislav Petkov wrote:
> On Sun, Aug 02, 2020 at 07:28:00PM +0200, Saheed Bolarinwa wrote:
> > Because the value ~0 has a meaning to some drivers and only
>
> No, ~0 means that the PCI read failed. For *every* PCI device I know.
Wait, I'm not convinced ye
On Sun, Aug 02, 2020 at 02:14:06PM -0500, Bjorn Helgaas wrote:
> Wait, I'm not convinced yet. I know that if a PCI read fails, you
> normally get ~0 data because the host bridge fabricates it to complete
> the CPU load.
>
> But what guarantees that a PCI config register cannot contain ~0?
Well,
On 2020/8/2 22:52, Jia-Ju Bai wrote:
> In qm_qp_ctx_cfg(), "sqc" and "aeqc" are mapped to streaming DMA:
> eqc_dma = dma_map_single(..., eqc, ...);
> ..
> aeqc_dma = dma_map_single(..., aeqc, ...);
Only sqc, cqc will be configured in qm_qp_ctx_cfg.
>
> Then "sqc" and "aeqc" are accesse
On 2020/8/3 9:12, Zhou Wang wrote:
On 2020/8/2 22:52, Jia-Ju Bai wrote:
In qm_qp_ctx_cfg(), "sqc" and "aeqc" are mapped to streaming DMA:
eqc_dma = dma_map_single(..., eqc, ...);
..
aeqc_dma = dma_map_single(..., aeqc, ...);
Only sqc, cqc will be configured in qm_qp_ctx_cfg.
T
Hi Linus:
API:
- Add support for allocating transforms on a specific NUMA Node.
- Introduce the flag CRYPTO_ALG_ALLOCATES_MEMORY for storage users.
Algorithms:
- Drop PMULL based ghash on arm64.
- Fixes for building with clang on x86.
- Add sha256 helper that does the digest in one go.
- Add SP
Hi All,
We have tunnel test scenario as below
IPsec tunnel gets created between
1. Our device 3000::::b25c:daff:fe67:f173
2. Gateway 3001::::0200:10ff:fe10:1161
There are 2 hosts behind the gateway
1. Host1 3002::::0200:10ff:fe10:1280
2
On Sun, Aug 02, 2020 at 02:14:06PM -0500, Bjorn Helgaas wrote:
> But what guarantees that a PCI config register cannot contain ~0?
> If there's something about that in the spec I'd love to know where it
> is because it would simplify a lot of things.
There isn't. An we even have cases like the NV
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