Re: crypto: marvell/CESA: Issues with non cache-line aligned buffers

2015-07-05 Thread Herbert Xu
On Fri, Jul 03, 2015 at 11:43:05AM +0200, Boris Brezillon wrote: > > We also noticed that the cra_alignmask fields were all set to 0 in the > CESA driver, but modifying them (setting them to ARCH_DMA_MINALIGN - 1) > does not seem to guarantee any alignment. > ITOH, the xxx_walk_xxx API seem to chec

Re: crypto: marvell/CESA: Issues with non cache-line aligned buffers

2015-07-05 Thread Herbert Xu
On Sat, Jul 04, 2015 at 03:33:55PM +0800, Herbert Xu wrote: > Note that I don't think we have a suitable helper for DMA-aligned > processing of SG lists. The ablkcipher_walk_* interface is mostly > identical to the blkcipher_walk_* interface. Actually I take that back. The ablkcipher_walk_* shou

Re: crypto: marvell/CESA: Issues with non cache-line aligned buffers

2015-07-03 Thread Andrew Lunn
> A few other things I notice when looking at this code: > > /* Not all platforms can gate the clock, so it is not >an error if the clock does not exists. */ > cp->clk = clk_get(&pdev->dev, NULL); > if (!IS_ERR(cp->clk)) > clk_prepare_enable(cp->

Re: crypto: marvell/CESA: Issues with non cache-line aligned buffers

2015-07-03 Thread Boris Brezillon
On Fri, 3 Jul 2015 10:58:07 +0100 Russell King - ARM Linux wrote: > On Fri, Jul 03, 2015 at 11:43:05AM +0200, Boris Brezillon wrote: > > Which led us to think that this could be related to a non cache-line > > aligned buffer problem: if we share the cache line with someone > > modifying its data

Re: crypto: marvell/CESA: Issues with non cache-line aligned buffers

2015-07-03 Thread Boris Brezillon
Hi Russel, On Fri, 3 Jul 2015 14:10:59 +0100 Russell King - ARM Linux wrote: > BTW, off-topic for this thread... but I notice from Mark Brown's builder > that mv_cesa is causing build errors in mainline now: > > arm-allmodconfig > ../drivers/crypto/mv_cesa.c:1037:2: error: implicit decl

Re: crypto: marvell/CESA: Issues with non cache-line aligned buffers

2015-07-03 Thread Russell King - ARM Linux
BTW, off-topic for this thread... but I notice from Mark Brown's builder that mv_cesa is causing build errors in mainline now: arm-allmodconfig ../drivers/crypto/mv_cesa.c:1037:2: error: implicit declaration of function 'of_get_named_gen_pool' [-Werror=implicit-function-declaration]

Re: crypto: marvell/CESA: Issues with non cache-line aligned buffers

2015-07-03 Thread Russell King - ARM Linux
On Fri, Jul 03, 2015 at 11:43:05AM +0200, Boris Brezillon wrote: > Which led us to think that this could be related to a non cache-line > aligned buffer problem: if we share the cache line with someone > modifying its data during the DMA transfer, we could experience data > loss when the cpu decide

crypto: marvell/CESA: Issues with non cache-line aligned buffers

2015-07-03 Thread Boris Brezillon
Hello, We've been facing a bug with the new CESA driver on armada 370 for a couple of days. Arnaud found out that this bug appeared when we fixed the req->src == req->dst case (by passing DMA_BIDIRECTIONAL when mapping the sg list instead of mapping the same sg list twice, once with the TO_DEVIC