> Subject: Re: [EXT] Re: [PATCH v2 2/3] drivers: crypto: add support for
> OCTEONTX2 CPT engine
>
> On Fri, Sep 04, 2020 at 04:36:29PM +, Sunil Kovvuri Goutham wrote:
> >
> >
> > > -Original Message-
> > > From: Herbert Xu
> > &g
-
> > cry...@vger.kernel.org; Suheil Chandran ;
> > Narayana Prasad Raju Athreya ; Sunil Kovvuri
> > Goutham ; Linu Cherian ;
> > Geethasowjanya Akula ; Jerin Jacob Kollanukkaran
> > ; Ard Biesheuvel
> > Subject: Re: [EXT] Re: [PATCH v2 2/3] drivers: crypto: add sup
; Goutham ; Linu Cherian ;
> Geethasowjanya Akula ; Jerin Jacob Kollanukkaran
> ; Ard Biesheuvel
> Subject: Re: [EXT] Re: [PATCH v2 2/3] drivers: crypto: add support for
> OCTEONTX2 CPT engine
>
> On Fri, Sep 04, 2020 at 02:14:34PM +, Srujana Challa wrote:
> >
> >
On Fri, Sep 04, 2020 at 02:14:34PM +, Srujana Challa wrote:
>
> Since LMT store is our platform specific, it cannot be generalized to all
> ARM64.
I'm not asking you to generalise it to all of ARM64. I'm asking
you to move this into a header file under arch/arm64 that can then
be shared by b
> Subject: [EXT] Re: [PATCH v2 2/3] drivers: crypto: add support for OCTEONTX2
> CPT engine
>
> External Email
>
> --
> On Fri, Sep 04, 2020 at 01:45:38PM +, Srujana Challa wrote:
> >
> > T
> Subject: Re: [PATCH v2 2/3] drivers: crypto: add support for OCTEONTX2 CPT
> engine
>
> On Fri, Aug 07, 2020 at 07:39:19PM +0530, Srujana Challa wrote:
> >
> > +#if defined(CONFIG_ARM64)
> > +static inline long otx2_lmt_flush(void *ioreg)
> > +{
> >
On Fri, Sep 04, 2020 at 01:45:38PM +, Srujana Challa wrote:
>
> This block of code is used for LMT store operations. The LMT store operation
> is specific to our platform, and this uses the "ldeor" instruction(which is
> actually an LSE atomic instruction available on v8.1 CPUs) targeting the
>
On Fri, Aug 07, 2020 at 07:39:19PM +0530, Srujana Challa wrote:
>
> +#if defined(CONFIG_ARM64)
> +static inline long otx2_lmt_flush(void *ioreg)
> +{
> + long result = 0;
> +
> + __asm__ volatile(".cpu generic+lse\n"
> + "ldeor xzr, %0, [%1]\n"
> +
On Fri, Aug 07, 2020 at 07:39:19PM +0530, Srujana Challa wrote:
>
> +/*
> + * On OcteonTX2 platform the parameter insts_num is used as a count of
> + * instructions to be enqueued. The valid values for insts_num are:
> + * 1 - 1 CPT instruction will be enqueued during LMTST operation
> + * 2 - 2 CP
On Fri, 7 Aug 2020 19:39:19 +0530 Srujana Challa wrote:
> Add support for the cryptographic acceleration unit (CPT) on
> OcteonTX2 CN96XX SoC.
Please address the W=1 C=1 build warnings
../drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c:475:51: warning: cast
removes address space '__iomem' of
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