On Tue, Feb 23, 2021 at 4:54 PM Dey, Megha wrote:
>
> Hi Andy,
>
> On 1/24/2021 8:23 AM, Andy Lutomirski wrote:
> > On Fri, Jan 22, 2021 at 11:29 PM Megha Dey wrote:
> >> Optimize crypto algorithms using AVX512 instructions - VAES and VPCLMULQDQ
> >> (first implemented on Intel's Icelake client a
Hi Andy,
On 1/24/2021 8:23 AM, Andy Lutomirski wrote:
On Fri, Jan 22, 2021 at 11:29 PM Megha Dey wrote:
Optimize crypto algorithms using AVX512 instructions - VAES and VPCLMULQDQ
(first implemented on Intel's Icelake client and Xeon CPUs).
These algorithms take advantage of the AVX512 registe
On 1/22/21 11:28 PM, Megha Dey wrote:
> Other implementations of these crypto algorithms are possible, which would
> result in lower crypto performance but would not cause collateral damage
> from frequency drops (AVX512L vs AVX512VL).
I don't think you told us anywhere what AVX512L and AVX512VL a
On Fri, Jan 22, 2021 at 11:29 PM Megha Dey wrote:
>
> Optimize crypto algorithms using AVX512 instructions - VAES and VPCLMULQDQ
> (first implemented on Intel's Icelake client and Xeon CPUs).
>
> These algorithms take advantage of the AVX512 registers to keep the CPU
> busy and increase memory ban
Optimize crypto algorithms using AVX512 instructions - VAES and VPCLMULQDQ
(first implemented on Intel's Icelake client and Xeon CPUs).
These algorithms take advantage of the AVX512 registers to keep the CPU
busy and increase memory bandwidth utilization. They provide substantial
(2-10x) improveme
