On 10/26/2017 08:34 AM, PrasannaKumar Muralidharan wrote:
This patch series rearranges functions such that forward declarations
becomes unnecessary. Remove those forward declaration.
Why?
The code churn and increase in difficulty of attribution are big
drawbacks to this sort of patch set.
On 02/21/2017 11:27 PM, Christoph Hellwig wrote:
On Tue, Feb 21, 2017 at 09:36:04AM -0800, David Daney wrote:
With respect to pci_enable_msix(), what do you recommend as a replacement?
pci_alloc_irq_vectors. In fact I have a tree ready for after -rc1
that removes pci_enable_msix() entirely
se an API that forces us to allocate 184 when only 80 are required.
Currently pci_enable_msix() allows an arbitrary set of MSI-X to be
requested, which exactly fits the requirements of our (non
crypto/cavium) hardware.
Thanks in advance for any insight you can provide,
David Daney
On Wed, F
On 02/14/2017 10:26 AM, Randy Dunlap wrote:
On 02/14/17 09:09, David Daney wrote:
On 02/14/2017 09:07 AM, Arnd Bergmann wrote:
The driver fails to build if MSI support is disabled:
In file included from /git/arm-soc/drivers/crypto/cavium/cpt/cptpf_main.c:18:0:
drivers/crypto/cavium/cpt
On 02/14/2017 09:07 AM, Arnd Bergmann wrote:
The driver fails to build if MSI support is disabled:
In file included from /git/arm-soc/drivers/crypto/cavium/cpt/cptpf_main.c:18:0:
drivers/crypto/cavium/cpt/cptpf.h:57:20: error: array type has incomplete
element type 'struct msix_entry'
struct
4b fc db ed 71 e0 ae c0 0a a4 8c 35
f0 eb 89 f9 8a 4b 52 59 6f 09 7c 01 3f 56 e7 c7 bf
000100
Signed-off-by: David Daney
---
drivers/char/hw_random/core.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/char/hw_random/core.c b/drivers/char/hw_random/core.c
index 6ce5ce8..87
.
Make the hwrng name unique by including the underlying device name.
Also remove spaces from the name to make it possible to switch devices
via the sysfs knobs.
Signed-off-by: David Daney
---
drivers/char/hw_random/cavium-rng-vf.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff
On 11/18/2016 07:00 AM, gcheri...@gmail.com wrote:
From: George Cherian
Enable the Physical Function diver for the Cavium Crypto Engine (CPT)
found in Octeon-tx series of SoC's. CPT is the Cryptographic Acceleration
Unit. CPT includes microcoded GigaCypher symmetric engines (SEs) and
asymmetric
es not. Since this is a RNG, the byte swapping is not
important, but it is a difference.
Because of this, I think it should be acceptable to stick with the loop
we currently have.
If the hwrng maintainers want to change the loop, to a readsq(), we
might investigate this more.
Thanks,
David
On 08/22/2016 07:36 AM, Bjorn Helgaas wrote:
Hi David & Omer,
On Fri, Aug 19, 2016 at 03:32:12PM -0700, Omer Khaliq wrote:
From: David Daney
Some hardware presents an incorrect SR-IOV Function Dependency Link,
add a function to allow this to be overridden in the PF driver for
such dev
crypto_shash_descsize(hash) is unbounded, then the stack
will overflow and ... BOOM!
David Daney
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On 11/04/2010 09:32 AM, Mark Allyn wrote:
Subject: [PATCH 1/1] crypto: api.c: adding doxygen comments to api
Do we really use doxygen in the kernel? Perhaps a subject line
containing the string 'kernel-doc' would be more accurate.
Reading kernel-doc-nano-HOWTO.txt will show you the proper f
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