On Thu, Sep 12, 2019 at 9:33 PM Maxime Ripard wrote:
>
> On Thu, Sep 12, 2019 at 09:26:27PM +0100, Chen-Yu Tsai wrote:
> > > >
> > > > clock-names:
> > > > items:
> > > > - const: ahb
> > > > - c
On Thu, Sep 12, 2019 at 10:37 AM Maxime Ripard wrote:
>
> Hi Corentin,
>
> On Wed, Sep 11, 2019 at 08:31:58PM +0200, Corentin Labbe wrote:
> > On Sat, Sep 07, 2019 at 07:01:16AM +0300, Maxime Ripard wrote:
> > > On Fri, Sep 06, 2019 at 08:45:45PM +0200, Corentin Labbe wrote:
> > > > This patch add
ntin
> Cc: sta...@vger.kernel.org
Confirmed the driver properly loads again.
Tested-by: Chen-Yu Tsai
> ---
> drivers/crypto/sunxi-ss/sun4i-ss-core.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/crypto/sunxi-ss/sun4i-ss-core.c
> b/drivers/crypto/sunxi-ss/sun4
A31/A31s have the same "Security System" crypto engine as A10/A20,
but with a separate reset control.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun6i-a31.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/ar
Later Allwinner SoCs split out the reset controls for individual modules
out of the clock gate controls. The "Security System" crypto engine is
no different.
Signed-off-by: Chen-Yu Tsai
---
Documentation/devicetree/bindings/crypto/sun4i-ss.txt | 4
1 file changed, 4 insertion
2 adds optional reset control support to the sunxi-ss driver.
Patch 3 enables the crypto engine on sun6i, by adding the module clock and
device node.
Regards
ChenYu
Chen-Yu Tsai (3):
crypto: sunxi-ss: Document optional reset control bindings
crypto: sunxi-ss: Add optional reset control
On sun6i and later platforms, the reset control is split out of the
clock gates. Add support for an optional reset control.
Signed-off-by: Chen-Yu Tsai
---
drivers/crypto/sunxi-ss/sun4i-ss-core.c | 22 ++
drivers/crypto/sunxi-ss/sun4i-ss.h | 2 ++
2 files changed, 24
Hi,
On Mon, Jun 9, 2014 at 6:59 PM, LABBE Corentin
wrote:
> Add support for the Security System included in Allwinner SoC A20.
> The Security System is a hardware cryptographic accelerator that support
> AES/MD5/SHA1/DES/3DES/PRNG algorithms.
>
> Signed-off-by: LABBE Corentin
> ---
> drivers/c