在 2025/5/28 下午5:53, Stefano Garzarella 写道:
On Wed, May 28, 2025 at 05:34:49PM +0800, Qunqin Zhao wrote:
在 2025/5/28 下午5:24, Qunqin Zhao 写道:
在 2025/5/28 下午5:00, Stefano Garzarella 写道:
On Wed, May 28, 2025 at 04:42:05PM +0800, Qunqin Zhao wrote:
在 2025/5/28 下午3:57, Stefano Garzarella 写道:
On Wed, May 28, 2025 at 07:15:18PM +0200, Jann Horn wrote:
> On Wed, May 28, 2025 at 6:46 PM Kees Cook wrote:
> > On Tue, May 27, 2025 at 11:14:27PM -0700, Eric Biggers wrote:
> > > If this new sanitizer is going to move forward, is there any sort of plan
> > > or
> > > guide for how to update co
On Wed, May 28, 2025 at 6:46 PM Kees Cook wrote:
> On Tue, May 27, 2025 at 11:14:27PM -0700, Eric Biggers wrote:
> > If this new sanitizer is going to move forward, is there any sort of plan or
> > guide for how to update code to be compatible with it? Specifically
> > considering
> > common sit
On Wed, May 28, 2025, at 18:45, Kees Cook wrote:
> On Tue, May 27, 2025 at 11:14:27PM -0700, Eric Biggers wrote:
>> On Wed, May 28, 2025 at 01:15:05PM +0800, kernel test robot wrote:
> I'm not sure how to enforce "don't enable this unless you're developing
> the Overflow Behavior Types" with curre
On Tue, May 27, 2025 at 11:14:27PM -0700, Eric Biggers wrote:
> [+Kees and linux-hardening]
>
> On Wed, May 28, 2025 at 01:15:05PM +0800, kernel test robot wrote:
> >
> >
> > Hello,
> >
> > by this commit, the config has below diff:
> >
> > ---
> > /pkg/linux/x86_64-randconfig-101-20250522/cl
Hi Linus,
Could you apply this, please? There shouldn't be any functional change,
rather it's a switch to using combined bit-barrier ops and lesser barriers.
A better way to do this might be to provide set_bit_release(), but the end
result would be much the same.
Thanks,
David
---
From: Herbert
On 28/05/2025 09:01, Qunqin Zhao wrote:
> Changes to Loongson TPM driver would be best reviewed by the Loongson
> crypto driver maintainers.
>
> Signed-off-by: Qunqin Zhao
> Reviewed-by: Huacai Chen
> Reviewed-by: Jarkko Sakkinen
> ---
> v8-v10: None
> v7: Added tag from Jarkko and Huacai
> v
On Wed, 28 May 2025 at 11:25, Qunqin Zhao wrote:
>
>
> 在 2025/5/28 下午5:00, Stefano Garzarella 写道:
> > On Wed, May 28, 2025 at 04:42:05PM +0800, Qunqin Zhao wrote:
> >>
> >> 在 2025/5/28 下午3:57, Stefano Garzarella 写道:
> +chip = tpmm_chip_alloc(dev, &tpm_loongson_ops);
> +if (IS_ERR
On Wed, May 28, 2025 at 04:42:05PM +0800, Qunqin Zhao wrote:
在 2025/5/28 下午3:57, Stefano Garzarella 写道:
+ chip = tpmm_chip_alloc(dev, &tpm_loongson_ops);
+ if (IS_ERR(chip))
+ return PTR_ERR(chip);
+ chip->flags = TPM_CHIP_FLAG_TPM2 | TPM_CHIP_FLAG_IRQ;
Why setting TPM_CHIP_FL
在 2025/5/28 下午3:57, Stefano Garzarella 写道:
+ chip = tpmm_chip_alloc(dev, &tpm_loongson_ops);
+ if (IS_ERR(chip))
+ return PTR_ERR(chip);
+ chip->flags = TPM_CHIP_FLAG_TPM2 | TPM_CHIP_FLAG_IRQ;
Why setting TPM_CHIP_FLAG_IRQ?
When tpm_engine completes TPM_CC* command,
the ha
On Wed, May 28, 2025 at 5:15 PM Yanteng Si wrote:
>
> 在 5/28/25 4:17 PM, Huacai Chen 写道:
> > On Wed, May 28, 2025 at 4:06 PM Qunqin Zhao wrote:
> >>
> >>
> >> 在 2025/5/28 下午3:17, Huacai Chen 写道:
> >>> Hi, Qunqin,
> >>>
> >>> As I said before, why the patch "MAINTAINERS: Add entry for Loongson
> >
On Wed, May 28, 2025 at 05:34:49PM +0800, Qunqin Zhao wrote:
在 2025/5/28 下午5:24, Qunqin Zhao 写道:
在 2025/5/28 下午5:00, Stefano Garzarella 写道:
On Wed, May 28, 2025 at 04:42:05PM +0800, Qunqin Zhao wrote:
在 2025/5/28 下午3:57, Stefano Garzarella 写道:
+ chip = tpmm_chip_alloc(dev, &tpm_loongson
在 2025/5/28 下午5:24, Qunqin Zhao 写道:
在 2025/5/28 下午5:00, Stefano Garzarella 写道:
On Wed, May 28, 2025 at 04:42:05PM +0800, Qunqin Zhao wrote:
在 2025/5/28 下午3:57, Stefano Garzarella 写道:
+ chip = tpmm_chip_alloc(dev, &tpm_loongson_ops);
+ if (IS_ERR(chip))
+ return PTR_ERR(chip);
在 2025/5/28 下午5:00, Stefano Garzarella 写道:
On Wed, May 28, 2025 at 04:42:05PM +0800, Qunqin Zhao wrote:
在 2025/5/28 下午3:57, Stefano Garzarella 写道:
+ chip = tpmm_chip_alloc(dev, &tpm_loongson_ops);
+ if (IS_ERR(chip))
+ return PTR_ERR(chip);
+ chip->flags = TPM_CHIP_FLAG_TPM2
在 5/28/25 4:17 PM, Huacai Chen 写道:
On Wed, May 28, 2025 at 4:06 PM Qunqin Zhao wrote:
在 2025/5/28 下午3:17, Huacai Chen 写道:
Hi, Qunqin,
As I said before, why the patch "MAINTAINERS: Add entry for Loongson
Security Module driver" is missing?
Hi, Huacai
https://lore.kernel.org/all/8e55801a-a
On Wed, May 28, 2025 at 4:06 PM Qunqin Zhao wrote:
>
>
> 在 2025/5/28 下午3:17, Huacai Chen 写道:
> > Hi, Qunqin,
> >
> > As I said before, why the patch "MAINTAINERS: Add entry for Loongson
> > Security Module driver" is missing?
>
> Hi, Huacai
>
> https://lore.kernel.org/all/8e55801a-a46e-58d5-cf84-2
在 2025/5/28 下午3:17, Huacai Chen 写道:
Hi, Qunqin,
As I said before, why the patch "MAINTAINERS: Add entry for Loongson
Security Module driver" is missing?
Hi, Huacai
https://lore.kernel.org/all/8e55801a-a46e-58d5-cf84-2ee8a733d...@loongson.cn/
Thanks,
Qunqin.
Huacai
On Wed, May 28, 2025
在 5/28/25 3:17 PM, Huacai Chen 写道:
Hi, Qunqin,
As I said before, why the patch "MAINTAINERS: Add entry for Loongson
Security Module driver" is missing?
Similar issues widely exist in the Loongarch mailing list.
The cause should be attributed to the mail server of Loongson.
It seems that Loong
On Wed, May 28, 2025 at 02:59:43PM +0800, Qunqin Zhao wrote:
Loongson Security Engine supports random number generation, hash,
symmetric encryption and asymmetric encryption. Based on these
encryption functions, TPM2 have been implemented in the Loongson
Security Engine firmware. This driver is r
Hi, Qunqin,
As I said before, why the patch "MAINTAINERS: Add entry for Loongson
Security Module driver" is missing?
Huacai
On Wed, May 28, 2025 at 2:59 PM Qunqin Zhao wrote:
>
> The Loongson Security Engine chip supports RNG, SM2, SM3 and SM4
> accelerator engines. Each engine have its own DMA
Changes to Loongson TPM driver would be best reviewed by the Loongson
crypto driver maintainers.
Signed-off-by: Qunqin Zhao
Reviewed-by: Huacai Chen
Reviewed-by: Jarkko Sakkinen
---
v8-v10: None
v7: Added tag from Jarkko and Huacai
v6: "tpm_lsse.c" -> "tpm_loongson"
v4-v5: None
MAINTAINERS
This patch adds an entry for Loongson crypto driver in the list of
maintainers.
Signed-off-by: Qunqin Zhao
Reviewed-by: Huacai Chen
---
v10: None
v9: Added loongson-se.c/.h to the entry.
v8: "RNG" --> "crypto"
v7: Added Huacai's tag
v5-v6: None
v4: Changed tile to "Add entry for ...".
Lowcas
Loongson Security Engine supports random number generation, hash,
symmetric encryption and asymmetric encryption. Based on these
encryption functions, TPM2 have been implemented in the Loongson
Security Engine firmware. This driver is responsible for copying data
into the memory visible to the firm
Loongson's Random Number Generator is found inside Loongson Security
Engine chip.
Co-developed-by: Yinggang Gu
Signed-off-by: Yinggang Gu
Signed-off-by: Qunqin Zhao
Reviewed-by: Huacai Chen
---
v10: In the init callback, select the device with the minimum users,
now the init callback shou
Loongson Security Engine chip supports RNG, SM2, SM3 and SM4 accelerator
engines. This is the base driver for other specific engine drivers.
Co-developed-by: Yinggang Gu
Signed-off-by: Yinggang Gu
Signed-off-by: Qunqin Zhao
Reviewed-by: Huacai Chen
---
v10: Cleanned up coding style.
v8: As ex
The Loongson Security Engine chip supports RNG, SM2, SM3 and SM4
accelerator engines. Each engine have its own DMA buffer provided
by the controller. The kernel cannot directly send commands to the
engine and must first send them to the controller, which will
forward them to the corresponding engin
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