poly1305-core.S is an auto-generated file, so it should be ignored.
Fixes: a11d055e7a64 ("crypto: mips/poly1305 - incorporate OpenSSL/CRYPTOGAMS
optimized implementation")
Signed-off-by: Ilya Lipnitskiy
Cc: Ard Biesheuvel
---
arch/mips/crypto/.gitignore | 2 ++
1 file changed, 2 insertions(+)
poly1305-core.S is an auto-generated file, so it should be ignored.
Fixes: a11d055e7a64 ("crypto: mips/poly1305 - incorporate OpenSSL/CRYPTOGAMS
optimized implementation")
Signed-off-by: Ilya Lipnitskiy
Cc: Ard Biesheuvel
---
arch/mips/crypto/.gitignore | 1 +
1 file changed, 1 insertion(+)
c
poly1305-core.S is an auto-generated file, so it should be ignored.
Signed-off-by: Ilya Lipnitskiy
Cc: Ard Biesheuvel
---
arch/mips/crypto/.gitignore | 1 +
1 file changed, 1 insertion(+)
create mode 100644 arch/mips/crypto/.gitignore
diff --git a/arch/mips/crypto/.gitignore b/arch/mips/crypt
Hello.
On Sat, Mar 27, 2021 at 05:48:01PM +0800, kernel test robot wrote:
> >> ERROR: modpost: "ZSTD_maxCLevel" [fs/f2fs/f2fs.ko] undefined!
Since f2fs can be built as a module, the following correction seems to
be needed:
```
diff --git a/lib/zstd/compress/zstd_compress.c
b/lib/zstd/compress/z
Hi!
> On 25.03.2021, at 06:26, Sumit Garg wrote:
>
> On Wed, 24 Mar 2021 at 19:37, Ahmad Fatoum wrote:
>>
>> Hello Sumit,
>>
>> On 24.03.21 11:47, Sumit Garg wrote:
>>> On Wed, 24 Mar 2021 at 14:56, Ahmad Fatoum wrote:
Hello Mimi,
On 23.03.21 19:07, Mimi Zohar wrote:
>>
The input data of the ECB (AES) algorithm needs to be aligned
with 16 bytes, and the input data of the XTS (AES) algorithm is
at least 16 bytes. Otherwise the SEC hardware will go wrong.
Signed-off-by: Longfang Liu
---
drivers/crypto/hisilicon/sec2/sec_crypto.c | 37 ++---
ctx_q_num is a module parameter set by the user to specify the
number of qp queues required to create a ctx.
When the number of qp queues allocated by PF or VF is less than
the ctx_q_num, an error will be reported when ctx is initialized
in kernel mode, which leads to the problem that the register
On 2021/3/27 17:29, Longfang Liu Wrote:
> ctx_q_num is a module parameter set by the user to specify the
> number of qp queues required to create a ctx.
>
> When the number of qp queues allocated by PF or VF is less than
> the ctx_q_num, an error will be reported when ctx is initialized
> in kerne
HPRE can only deal with src_data smaller than 'p' in 'CURVE25519'
algorithm, but 'rfc7748' says:
'Implementations MUST accept non-canonical values and process them as
if they had been reduced modulo the field prime'
So we get its modulus to p, and then deal it with HPRE.
Signed-off-by: Meng Yu
--
the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Nick-Terrell/Update-to-zstd-1-4-10/20210327-031827
base:
https://git.kernel.o
The input data of the ECB (AES) algorithm needs to be aligned
with 16 bytes, and the input data of the XTS (AES) algorithm is
at least 16 bytes. Otherwise the SEC hardware will go wrong.
Signed-off-by: Longfang Liu
---
drivers/crypto/hisilicon/sec2/sec_crypto.c | 37 ++---
ctx_q_num is a module parameter set by the user to specify the
number of qp queues required to create a ctx.
When the number of qp queues allocated by PF or VF is less than
the ctx_q_num, an error will be reported when ctx is initialized
in kernel mode, which leads to the problem that the register
'xx_debugfs_init' check if debugfs opened.
Signed-off-by: Hui Tang
---
drivers/crypto/hisilicon/hpre/hpre_main.c | 5 -
drivers/crypto/hisilicon/qm.c | 3 +++
drivers/crypto/hisilicon/sec2/sec_main.c | 5 -
drivers/crypto/hisilicon/zip/zip_main.c | 3 +++
4 files changed,
It has newline already by sysfs, so delete redundant '\n'
Signed-off-by: Hui Tang
---
drivers/crypto/hisilicon/hpre/hpre_main.c | 4 ++--
drivers/crypto/hisilicon/sec2/sec_main.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/hisilicon/hpre/hpre_main.c
b/
'hpre_cfg_by_dsm' has checked and printed error path, so it is not
necessary at all.
Signed-off-by: Hui Tang
---
drivers/crypto/hisilicon/hpre/hpre_main.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/crypto/hisilicon/hpre/hpre_main.c
b/drivers/crypto/hisilicon
s/shoul/should/
Signed-off-by: Hui Tang
---
drivers/crypto/hisilicon/hpre/hpre_main.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/crypto/hisilicon/hpre/hpre_main.c
b/drivers/crypto/hisilicon/hpre/hpre_main.c
index f2605c4..8aae921 100644
--- a/drivers/crypto/hi
We must confirm the PASID is disabled before using no-sva mode.
Signed-off-by: Hui Tang
---
drivers/crypto/hisilicon/hpre/hpre_main.c | 43 +--
1 file changed, 18 insertions(+), 25 deletions(-)
diff --git a/drivers/crypto/hisilicon/hpre/hpre_main.c
b/drivers/crypto/
The operations about 'sqe' are different on some hardwares. Add a struct
'hisi_zip_sqe_ops' to describe the operations in a hardware. And choose the
'ops' in 'hisi_zip_acomp_init' according to the hardware.
Signed-off-by: Yang Shen
---
drivers/crypto/hisilicon/zip/zip_crypto.c | 141
This patch changes nothing about functions except location in order to make
code logic clearly.
This adjustment follows three principles:
1.The called functions are listed in order above the calling functions.
2.The paired functions are next to each other.
3.Logically similar functions are placed
In Kunpeng930, some field meanings in 'sqe' are changed, so driver need to
distinguish the type on different platform.
To avoid checking the platform everytime when driver fills the 'sqe', add a
struct 'hisi_zip_sqe_ops' to describe the 'sqe' operations. The driver only
need to choose the 'ops' on
The Kunpeng930 changes some field meanings in 'sqe'. So add a new
'hisi_zip_sqe_ops' to describe the 'sqe' operations.
Signed-off-by: Yang Shen
---
drivers/crypto/hisilicon/zip/zip.h| 1 +
drivers/crypto/hisilicon/zip/zip_crypto.c | 25 +
2 files changed, 26 inse
Some fields of 'hisi_zip_sqe' are unused, and some fields have misc
utilities. So add comments for used fields and make others unnamed.
Signed-off-by: Yang Shen
---
drivers/crypto/hisilicon/zip/zip.h| 45 ++-
drivers/crypto/hisilicon/zip/zip_crypto.c | 4 +--
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