Hi Linus:
API:
- Add speed testing on 1420-byte blocks for networking.
Algorithms:
- Improve performance of chacha on ARM for network packets.
- Improve performance of aegis128 on ARM for network packets.
Drivers:
- Add support for Keem Bay OCS AES/SM4.
- Add support for QAT 4xxx devices.
- E
The driver crc32c-intel match CPUs supporting X86_FEATURE_XMM4_2.
On platforms with Zhaoxin CPUs supporting this X86 feature, when
crc32c-intel and crc32c-generic are both registered, system will
use crc32c-intel because its .cra_priority is greater than
crc32c-generic.
When doing lmbench3 Create
Hi all,
Today's linux-next merge of the drm tree got a conflict in:
MAINTAINERS
between commit:
885743324513 ("crypto: keembay - Add support for Keem Bay OCS AES/SM4")
from the crypto tree and commit:
ed794057b052 ("drm/kmb: Build files for KeemBay Display driver")
from the drm tree.
On 12/12/2020 18:54, Ard Biesheuvel wrote:
> On Sat, 12 Dec 2020 at 10:36, Ard Biesheuvel wrote:
>>
>> On Fri, 11 Dec 2020 at 20:07, Eric Biggers wrote:
>>>
>>> On Fri, Dec 11, 2020 at 07:29:04PM +0800, Tony W Wang-oc wrote:
The driver crc32c-intel match CPUs supporting X86_FEATURE_XMM4_2
On 12/12/2020 01:43, Eric Biggers wrote:
> On Fri, Dec 11, 2020 at 07:29:04PM +0800, Tony W Wang-oc wrote:
>> The driver crc32c-intel match CPUs supporting X86_FEATURE_XMM4_2.
>> On platforms with Zhaoxin CPUs supporting this X86 feature, When
>> crc32c-intel and crc32c-generic are both registered,
On Sun, Dec 13, 2020 at 06:23:06PM -0800, Eric Biggers wrote:
>
> This part doesn't seem to be true, since the chacha implementations don't
> implement the "output IV" thing. It's only cbc and ctr that do (or at least
> those are the only algorithms it's tested for).
If this algorithm can be used
On Sun, Dec 13, 2020 at 03:39:29PM +0100, Ard Biesheuvel wrote:
> This violates the skcipher API, which requires that the output IV is suitable
> for handling more input as long as the preceding input has been presented in
> round multiples of the block size.
This part doesn't seem to be true, si
On Wed, 2020-12-09 at 21:25 -0600, Brijesh Singh wrote:
> Noted, I will send v2 with these fixed.
I ran a test on this. It turns out for rome systems you need firmware
md_sev_fam17h_model3xh_0.24b0A (or later) installed to get this and the
QEMU patch with the base64 decoding fixed, but with that
Acked-by: Jamie Iles
for the series. Intel EOLd this product now, good idea to remove it.
Thanks,
Jamie
On Thu, Dec 10, 2020 at 02:03:11PM -0600, Rob Herring wrote:
> PicoXcell has had nothing but treewide cleanups for at least the last 8
> years and no signs of activity. The most recent acti
Commit 86cd97ec4b943af3 ("crypto: arm/chacha-neon - optimize for non-block
size multiples") refactored the chacha block handling in the glue code in
a way that may result in the counter increment to be omitted when calling
chacha_block_xor_neon() to process a full block. This violates the skcipher
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