If the parameter type provided to adf_cfg_add_key_value_param()
is invalid, return -EINVAL instead of -1 that is treated as -EPERM and
may confuse.
Suggested-by: Andy Shevchenko
Signed-off-by: Giovanni Cabiddu
Reviewed-by: Andy Shevchenko
---
drivers/crypto/qat/qat_common/adf_cfg.c | 2 +-
1 f
Allow for crypto instances to be configured with symmetric crypto rings
that belong to a bank that is different from the one where asymmetric
crypto rings are located.
This is to allow for devices with banks made of a single ring pair.
In these, crypto instances will be composed of two separate ba
Refactor function qat_crypto_create_instances() to propagate errors to
the caller.
Suggested-by: Andy Shevchenko
Signed-off-by: Giovanni Cabiddu
Reviewed-by: Andy Shevchenko
---
drivers/crypto/qat/qat_common/qat_crypto.c | 68 +-
1 file changed, 41 insertions(+), 27 deletio
Remove superfluous casts to void* in function qat_crypto_dev_config().
Suggested-by: Andy Shevchenko
Signed-off-by: Giovanni Cabiddu
Reviewed-by: Andy Shevchenko
---
drivers/crypto/qat/qat_common/qat_crypto.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --
Refactor function qat_crypto_dev_config() to propagate errors to
the caller.
Suggested-by: Andy Shevchenko
Signed-off-by: Giovanni Cabiddu
Reviewed-by: Andy Shevchenko
---
drivers/crypto/qat/qat_common/qat_crypto.c | 67 +-
1 file changed, 41 insertions(+), 26 deletions(-)
Change type of ae_mask in adf_hw_device_data to allow for devices with
more than 16 Acceleration Engines (AEs).
Signed-off-by: Giovanni Cabiddu
Reviewed-by: Wojciech Ziemba
Reviewed-by: Fiona Trahe
Reviewed-by: Andy Shevchenko
---
drivers/crypto/qat/qat_common/adf_accel_devices.h | 2 +-
1 fi
If a key is not found in the internal key value storage, return -ENODATA
instead of -1 that is treated as -EPERM and may confuse.
Suggested-by: Andy Shevchenko
Signed-off-by: Giovanni Cabiddu
Reviewed-by: Andy Shevchenko
---
drivers/crypto/qat/qat_common/adf_cfg.c | 2 +-
1 file changed, 1 ins
Call the function configure_iov_threads(), adf_enable_vf2pf_interrupts()
and adf_pf2vf_notify_restarting() only if present in the struct
adf_hw_device_data of the device.
This is to allow for QAT drivers that do not implement those functions.
Signed-off-by: Giovanni Cabiddu
Reviewed-by: Wojciech
Replace hardcoded value of the bank interrupt clear flag mask with a
value calculated on the fly which is based on the number of rings
present in a bank. This is to support devices that have a number of
rings per bank different than 16.
Signed-off-by: Giovanni Cabiddu
Reviewed-by: Wojciech Ziemba
The number of AE2FUNC_MAP registers is different in every QAT device
(c62x, c3xxx and dh895xcc) although the logic and the register offsets
are the same across devices.
This patch separates the logic that configures the iov threads in a
common function that takes as input the number of AE2FUNC_MAP
Enable acceleration engines (AEs) and accelerators based on soft straps
and fuses. When looping with a number of AEs or accelerators, ignore the
ones that are disabled.
This patch is based on earlier work done by Conor McLoughlin.
Signed-off-by: Giovanni Cabiddu
Reviewed-by: Fiona Trahe
Reviewe
Abstract writes to the service arbiter enable register.
This is in preparation for the introduction of the qat_4xxx driver since
the arbitration enable register differes between QAT GEN2 and QAT GEN4
devices.
Signed-off-by: Giovanni Cabiddu
Reviewed-by: Wojciech Ziemba
Reviewed-by: Maksim Lukos
From: Marco Chiappero
Do IV update calculations in software for AES-CBC and AES-CTR.
This allows to embed the IV on the request descriptor and removes the
allocation of the IV buffer in the data path.
In addition, this change allows the support of QAT devices that are not
capable of updating th
Rename occurrences of ME in the admin module with the acronym AE
(Acceleration Engine) as the two are equivalent.
This is to keep a single acronym for engined in the codebase and
follow the documentation in https://01.org/intel-quickassist-technology.
Signed-off-by: Giovanni Cabiddu
Reviewed-by:
Extend admin contansts table to support QAT GEN4 devices.
This change does not affect QAT GEN2 devices (c62x, c3xxx and dh895xcc)
as the table was extended in an unused area which is not referenced by
any of those drivers and devices.
Signed-off-by: Giovanni Cabiddu
Reviewed-by: Fiona Trahe
Rev
Abstract the implementation of BUILD_RING_BASE_ADDR.
This is in preparation for the introduction of the qat_4xxx driver since
the value of the ring base differs between QAT GEN2 and QAT GEN4
devices.
Signed-off-by: Giovanni Cabiddu
Reviewed-by: Wojciech Ziemba
Reviewed-by: Maksim Lukoshkov
Rev
Abstract access to transport CSRs and move generation specific code into
adf_gen2_hw_data.c in preparation for the introduction of the qat_4xxx
driver.
Signed-off-by: Giovanni Cabiddu
Reviewed-by: Fiona Trahe
Reviewed-by: Wojciech Ziemba
Reviewed-by: Andy Shevchenko
---
.../crypto/qat/qat_c3x
Introduce admin AE mask. If this mask set, the fw constant message is
sent only to engines that belong to that set, otherwise it is sent to
all engines.
This is in preparation for the qat_4xxx driver where the constant message
should be sent only to admin engines.
In GEN2 devices (c62x, c3xxx and
From: Ahsan Atta
This change is to allow support for QAT devices that may not have 16
rings per bank.
The rings structure in bank is allocated dynamically based on the number
of banks supported by a device.
Note that in the error path in adf_init_bank(), ring->inflights is set
to NULL after the
Replace occurrences of the pattern GENMASK_ULL(var - 1, 0)) with
BIT_ULL(var) - 1 since it produces better code and it is easier to read.
Suggested-by: Andy Shevchenko
Signed-off-by: Giovanni Cabiddu
Reviewed-by: Andy Shevchenko
---
drivers/crypto/qat/qat_common/adf_sriov.c | 2 +-
This set is an initial rework of the QAT driver in preparation for the
inclusion of the qat_4xxx driver (QAT GEN4).
Summary of changes:
* IV update logic moved to software to remove allocation of the IV
buffer in the data-path and allow for devices that are not capable
of updating it whe
Move gen2 specific transport macros to adf_gen2_hw_data.c.
Signed-off-by: Giovanni Cabiddu
Reviewed-by: Fiona Trahe
Reviewed-by: Wojciech Ziemba
Reviewed-by: Andy Shevchenko
---
.../crypto/qat/qat_common/adf_gen2_hw_data.c | 1 -
.../crypto/qat/qat_common/adf_gen2_hw_data.h | 68 ++
WQCFG registers contain the correct values after reset in all
generations of QAT. No need to write into them.
Signed-off-by: Giovanni Cabiddu
Reviewed-by: Fiona Trahe
Reviewed-by: Wojciech Ziemba
Reviewed-by: Andy Shevchenko
---
drivers/crypto/qat/qat_common/adf_hw_arbiter.c | 13
Introduce the function adf_hw_dev_has_crypto() that returns true if a
device supports symmetric crypto, asymmetric crypto and authentication
services.
If a device has crypto capabilities, add crypto instances to the
configuration.
This is done since the function that allows to retrieve crypto
insta
Remove the unused macros ADF_ARB_WTR_SIZE, ADF_ARB_WTR_OFFSET
and ADF_ARB_RO_EN_OFFSET.
These macros were left in commit 34074205bb9f ("crypto: qat - remove
redundant arbiter configuration") that removed the logic that used those
defines.
Signed-off-by: Giovanni Cabiddu
Reviewed-by: Fiona Trahe
Abstract access to admin interface and move generation specific code into
adf_gen2_hw_data.c in preparation for the introduction of the qat_4xxx
driver.
Signed-off-by: Giovanni Cabiddu
Reviewed-by: Fiona Trahe
Reviewed-by: Wojciech Ziemba
Reviewed-by: Andy Shevchenko
---
.../crypto/qat/qat_c3
The arbiter configuration, the offset to the arbiter config CSR and the
offset to the worker thread to service arbiter CSR are going to be
different in QAT GEN4 devices although the logic that uses them is the
same across all QAT generations.
This patch reworks the gen-specific parts of the arbite
Replace constant 0xULL with GENMASK_ULL(63, 0) and
0x with GENMASK(31, 0) as they are masks.
This makes code less error prone.
Suggested-by: Andy Shevchenko
Signed-off-by: Giovanni Cabiddu
Reviewed-by: Andy Shevchenko
---
drivers/crypto/qat/qat_common/adf_gen2_hw_data.h
Call adf_set_fw_constants() before adf_init_ae().
This is required by QAT GEN4 devices, which expect that the
FW_CONSTANTS_CFG command is sent to the admin AEs before the FW_INIT_AE
command.
Swapping the order of the two commands (FW_INIT_AE and FW_CONSTANTS_CFG)
is allowed in QAT GEN2 devices as
From: Marco Chiappero
Add logic to detect device capabilities for c62x, c3xxx and dh895xcc.
Read fuses, straps and legfuses CSRs and build the device capabilities
mask. This will be used to understand if a certain service is supported
by a device.
This patch is based on earlier work done by Con
Enable arbitration on the TX ring only after the RX ring is programmed.
Before this change, arbitration was enabled on the TX ring before the RX
ring was programmed allowing the HW to process a request before having
the ring pair configured.
With this change, the arbitration logic is programmed on
Add packed attribute to the structures icp_qat_fw_init_admin_req and
icp_qat_fw_init_admin_resp as they are accessed by firmware.
Signed-off-by: Giovanni Cabiddu
Reviewed-by: Fiona Trahe
Reviewed-by: Wojciech Ziemba
Reviewed-by: Andy Shevchenko
---
drivers/crypto/qat/qat_common/icp_qat_fw_ini
+++ Daniel Jordan [08/10/20 13:32 -0400]:
Corentin hit the following workqueue warning when running with
CRYPTO_MANAGER_EXTRA_TESTS:
WARNING: CPU: 2 PID: 147 at kernel/workqueue.c:1473 __queue_work+0x3b8/0x3d0
Modules linked in: ghash_generic
CPU: 2 PID: 147 Comm: modprobe Not tainted
5.
documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Srujana-Challa/octeontx2-af-add-debugfs-entries-for-CPT-block/20201012-161457
base: https://git.kernel.org/pub/scm/linux/kernel/git/horms/ipvs.git master
config: arm64-randconfig-r001-20201012
CPT RVU Local Functions(LFs) needs to be attached to the
PF/VF to submit the instructions to CPT.
This patch adds the interface to initialize and attach
the LFs. It also adds interface to register the LF's
interrupts.
Signed-off-by: Suheil Chandran
Signed-off-by: Srujana Challa
---
drivers/cryp
Attach LFs to CPT VF to process the crypto requests and register
LF interrupts.
Signed-off-by: Suheil Chandran
Signed-off-by: Srujana Challa
---
drivers/crypto/marvell/octeontx2/Makefile | 2 +-
.../marvell/octeontx2/otx2_cpt_reqmgr.h | 145 +
drivers/crypto/marvell/octeontx2/ot
Adds support to get engine capabilities and adds a new mailbox
to share the engine capabilities to CPT VFIO drivers.
Signed-off-by: Suheil Chandran
Signed-off-by: Srujana Challa
---
.../marvell/octeontx2/otx2_cpt_common.h | 36
.../marvell/octeontx2/otx2_cpt_reqmgr.h | 51 +++
Add support for the Marvell OcteonTX2 CPT virtual function
driver. This patch includes probe, PCI specific initialization
and interrupt handling.
Signed-off-by: Suheil Chandran
Signed-off-by: Srujana Challa
---
drivers/crypto/marvell/octeontx2/Makefile | 4 +-
.../marvell/octeontx2/otx2_c
CPT offload module utilises the linux crypto framework to offload
crypto processing. This patch registers supported algorithms by
calling registration functions provided by the kernel crypto API.
The module currently supports:
- AES block cipher in CBC,ECB,XTS and CFB mode.
- 3DES block cipher in
Add new mailbox message to configure a LF for RX inline-IPsec.
This message is added to serve Marvell CPT VFIO driver, since
a VF can not send mailbox messages to admin function(AF)
directly.
Signed-off-by: Suheil Chandran
Signed-off-by: Srujana Challa
---
.../marvell/octeontx2/otx2_cpt_common.
In the resource virtualization unit (RVU) each of the PF and AF
(admin function) share a 64KB of reserved memory region for
communication. This patch initializes PF <=> AF mailbox IRQs,
registers handlers for processing these communication messages.
Signed-off-by: Suheil Chandran
Signed-off-by: S
CPT includes microcoded GigaCypher symmetric engines(SEs), IPsec
symmetric engines(IEs), and asymmetric engines (AEs).
Each engine receives CPT instructions from the engine groups it has
subscribed to. This patch loads microcode, configures three engine
groups(one for SEs, one for IEs and one for A
Adds 'sriov_configure' to enable/disable virtual functions (VFs).
Also Initializes VF<=>PF mailbox IRQs, register handlers for
processing these mailbox messages.
Admin function (AF) handles resource allocation and configuration for
PFs and their VFs. PFs request the AF directly, via mailboxes.
Unl
Adds skeleton for the Marvell OcteonTX2 CPT physical function
driver which includes probe, PCI specific initialization and
hardware register defines.
RVU defines are present in AF driver
(drivers/net/ethernet/marvell/octeontx2/af), header files from
AF driver are included here to avoid duplication.
On OcteonTX2 SoC, the admin function (AF) is the only one with all
priviliges to configure HW and alloc resources, PFs and it's VFs
have to request AF via mailbox for all their needs. This patch adds
a mailbox interface for CPT PFs and VFs to allocate resources
for cryptography and inline-IPsec.
In
On OcteonTX2 platform CPT instruction enqueue and NIX
packet send are only possible via LMTST operations which
uses LDEOR instruction. This patch moves lmt flush
function from OcteonTX2 nic driver to include/linux/soc
since it will be used by OcteonTX2 CPT and NIC driver for
LMTST.
Signed-off-by:
This series introduces crypto(CPT) drivers(PF & VF) for Marvell OcteonTX2
CN96XX Soc.
OcteonTX2 SOC's resource virtualization unit (RVU) supports multiple
physical and virtual functions. Each of the PF/VF's functionality is
determined by what kind of resources are attached to it. When the CPT
bloc
Add entries to debugfs at /sys/kernel/debug/octeontx2/cpt.
cpt_pc: dump cpt performance HW registers.
Usage: cat /sys/kernel/debug/octeontx2/cpt/cpt_pc
cpt_engines_sts: show cpt engines current state (busy/free status)
Usage:
echo "AE/SE/IE/all" > /sys/kernel/debug/octeontx2/cpt/cpt_engines_sts
CPT offload module utilises the linux crypto framework to offload
crypto processing. This patch registers supported algorithms by
calling registration functions provided by the kernel crypto API.
The module currently supports:
- AES block cipher in CBC,ECB,XTS and CFB mode.
- 3DES block cipher in
Add support for the Marvell OcteonTX2 CPT virtual function
driver. This patch includes probe, PCI specific initialization
and interrupt handling.
Signed-off-by: Srujana Challa
---
drivers/crypto/marvell/octeontx2/Makefile | 4 +-
.../marvell/octeontx2/otx2_cpt_common.h | 1 +
.../m
Attach LFs to CPT VF to process the crypto requests and register
LF interrupts.
Signed-off-by: Srujana Challa
---
drivers/crypto/marvell/octeontx2/Makefile | 2 +-
.../marvell/octeontx2/otx2_cpt_reqmgr.h | 145 +
drivers/crypto/marvell/octeontx2/otx2_cptlf.h | 7 +
.../marvell/
CPT RVU Local Functions(LFs) needs to be attached to the
PF/VF to submit the instructions to CPT.
This patch adds the interface to initialize and attach
the LFs. It also adds interface to register the LF's
interrupts.
Signed-off-by: Srujana Challa
---
drivers/crypto/marvell/octeontx2/Makefile
CPT includes microcoded GigaCypher symmetric engines(SEs), IPsec
symmetric engines(IEs), and asymmetric engines (AEs).
Each engine receives CPT instructions from the engine groups it has
subscribed to. This patch loads microcode, configures three engine
groups(one for SEs, one for IEs and one for A
Add new mailbox message to configure a LF for RX inline-IPsec.
This message is added to serve Marvell CPT VFIO driver, since
a VF can not send mailbox messages to admin function(AF)
directly.
Signed-off-by: Srujana Challa
---
.../marvell/octeontx2/otx2_cpt_common.h | 12 +++
drivers/crypto
Adds support to get engine capabilities and adds a new mailbox
to share the engine capabilities to CPT VFIO drivers.
Signed-off-by: Srujana Challa
---
.../marvell/octeontx2/otx2_cpt_common.h | 36
.../marvell/octeontx2/otx2_cpt_reqmgr.h | 51 ++
drivers/crypto/marvell/octe
In the resource virtualization unit (RVU) each of the PF and AF
(admin function) share a 64KB of reserved memory region for
communication. This patch initializes PF <=> AF mailbox IRQs,
registers handlers for processing these communication messages.
Signed-off-by: Srujana Challa
---
drivers/cryp
On OcteonTX2 SoC, the admin function (AF) is the only one with all
priviliges to configure HW and alloc resources, PFs and it's VFs
have to request AF via mailbox for all their needs. This patch adds
a mailbox interface for CPT PFs and VFs to allocate resources
for cryptography and inline-IPsec.
In
Adds 'sriov_configure' to enable/disable virtual functions (VFs).
Also Initializes VF<=>PF mailbox IRQs, register handlers for
processing these mailbox messages.
Admin function (AF) handles resource allocation and configuration for
PFs and their VFs. PFs request the AF directly, via mailboxes.
Unl
Adds skeleton for the Marvell OcteonTX2 CPT physical function
driver which includes probe, PCI specific initialization and
hardware register defines.
RVU defines are present in AF driver
(drivers/net/ethernet/marvell/octeontx2/af), header files from
AF driver are included here to avoid duplication.
Add entries to debugfs at /sys/kernel/debug/octeontx2/cpt.
cpt_pc: dump cpt performance HW registers.
Usage: cat /sys/kernel/debug/octeontx2/cpt/cpt_pc
cpt_engines_sts: show cpt engines current state (busy/free status)
Usage:
echo "AE/SE/IE/all" > /sys/kernel/debug/octeontx2/cpt/cpt_engines_sts
On OcteonTX2 platform CPT instruction enqueue and NIX
packet send are only possible via LMTST operations which
uses LDEOR instruction. This patch moves lmt flush
function from OcteonTX2 nic driver to include/linux/soc
since it will be used by OcteonTX2 CPT and NIC driver for
LMTST.
Signed-off-by:
This series introduces crypto(CPT) drivers(PF & VF) for Marvell OcteonTX2
CN96XX Soc.
OcteonTX2 SOC's resource virtualization unit (RVU) supports multiple
physical and virtual functions. Each of the PF/VF's functionality is
determined by what kind of resources are attached to it. When the CPT
bloc
I am sorry, please ignore this version of series, it was sent by mistake
without removing Gerrit Change IDs.
Thanks,
Srujana
> This series introduces crypto(CPT) drivers(PF & VF) for Marvell OcteonTX2
> CN96XX Soc.
>
> OcteonTX2 SOC's resource virtualization unit (RVU) supports multiple
> physi
CPT offload module utilises the linux crypto framework to offload
crypto processing. This patch registers supported algorithms by
calling registration functions provided by the kernel crypto API.
The module currently supports:
- AES block cipher in CBC,ECB,XTS and CFB mode.
- 3DES block cipher in
CPT RVU Local Functions(LFs) needs to be attached to the
PF/VF to submit the instructions to CPT.
This patch adds the interface to initialize and attach
the LFs. It also adds interface to register the LF's
interrupts.
Change-Id: I6a674bab7f905de63fed0a9b611ac4d69baa164f
Signed-off-by: Srujana Chal
Attach LFs to CPT VF to process the crypto requests and register
LF interrupts.
Change-Id: Idd9b8ff9a435d9dfc2591f17a84d2f96206dd994
Signed-off-by: Srujana Challa
---
drivers/crypto/marvell/octeontx2/Makefile | 2 +-
.../marvell/octeontx2/otx2_cpt_reqmgr.h | 145 +
drivers/crypto
Adds support to get engine capabilities and adds a new mailbox
to share the engine capabilities to CPT VFIO drivers.
Change-Id: Ic43320c02ca4595b5b82f1da9c7d3a070f046f55
Signed-off-by: Srujana Challa
---
.../marvell/octeontx2/otx2_cpt_common.h | 36
.../marvell/octeontx2/otx2_cpt_req
CPT includes microcoded GigaCypher symmetric engines(SEs), IPsec
symmetric engines(IEs), and asymmetric engines (AEs).
Each engine receives CPT instructions from the engine groups it has
subscribed to. This patch loads microcode, configures three engine
groups(one for SEs, one for IEs and one for A
Add new mailbox message to configure a LF for RX inline-IPsec.
This message is added to serve Marvell CPT VFIO driver, since
a VF can not send mailbox messages to admin function(AF)
directly.
Change-Id: I66c984eb3a865a28d59952e7210319c669ef9e6c
Signed-off-by: Srujana Challa
---
.../marvell/octeo
Add support for the Marvell OcteonTX2 CPT virtual function
driver. This patch includes probe, PCI specific initialization
and interrupt handling.
Change-Id: Ib0c81fcc7c0d43144463c37e7ea0e954bafe4b62
Signed-off-by: Srujana Challa
---
drivers/crypto/marvell/octeontx2/Makefile | 4 +-
.../mar
Add entries to debugfs at /sys/kernel/debug/octeontx2/cpt.
cpt_pc: dump cpt performance HW registers.
Usage: cat /sys/kernel/debug/octeontx2/cpt/cpt_pc
cpt_engines_sts: show cpt engines current state (busy/free status)
Usage:
echo "AE/SE/IE/all" > /sys/kernel/debug/octeontx2/cpt/cpt_engines_sts
On OcteonTX2 SoC, the admin function (AF) is the only one with all
priviliges to configure HW and alloc resources, PFs and it's VFs
have to request AF via mailbox for all their needs. This patch adds
a mailbox interface for CPT PFs and VFs to allocate resources
for cryptography and inline-IPsec.
In
This series introduces crypto(CPT) drivers(PF & VF) for Marvell OcteonTX2
CN96XX Soc.
OcteonTX2 SOC's resource virtualization unit (RVU) supports multiple
physical and virtual functions. Each of the PF/VF's functionality is
determined by what kind of resources are attached to it. When the CPT
bloc
Adds 'sriov_configure' to enable/disable virtual functions (VFs).
Also Initializes VF<=>PF mailbox IRQs, register handlers for
processing these mailbox messages.
Admin function (AF) handles resource allocation and configuration for
PFs and their VFs. PFs request the AF directly, via mailboxes.
Unl
In the resource virtualization unit (RVU) each of the PF and AF
(admin function) share a 64KB of reserved memory region for
communication. This patch initializes PF <=> AF mailbox IRQs,
registers handlers for processing these communication messages.
Change-Id: I9826d1703a1a19c347c9e3f3cd6a395c5a64
Adds skeleton for the Marvell OcteonTX2 CPT physical function
driver which includes probe, PCI specific initialization and
hardware register defines.
RVU defines are present in AF driver
(drivers/net/ethernet/marvell/octeontx2/af), header files from
AF driver are included here to avoid duplication.
On OcteonTX2 platform CPT instruction enqueue and NIX
packet send are only possible via LMTST operations which
uses LDEOR instruction. This patch moves lmt flush
function from OcteonTX2 nic driver to include/linux/soc
since it will be used by OcteonTX2 CPT and NIC driver for
LMTST.
Change-Id: I148
77 matches
Mail list logo
