Adjust some tiny coding problems and fix a bug of DH algorithm.
Changes since v1:
Remove 'u64' cast in 'cpu_to_le64';
Meng Yu (3):
crypto: hisilicon/hpre - remove useless code
crypto: hisilicon/hpre - adjust some coding style
crypto: hisilicon/hpre - fix a bug in dh algorithm
drivers/cryp
From: Meng Yu
1. Remove unused member 'debug_root' in 'struct hpre_debug';
2. The u64 cast is redundant in 'cpu_to_le64'.
Fixes: 848974151618("crypto: hisilicon - Add debugfs for HPRE")
Fixes: dadbe4c11753("crypto: hisilicon/hpre - update debugfs ...")
Signed-off-by: Meng Yu
Reviewed-by: Zaibo
From: Meng Yu
Adjust some coding style to make code aligned.
Signed-off-by: Meng Yu
Reviewed-by: Zaibo Xu
---
drivers/crypto/hisilicon/hpre/hpre_crypto.c | 13 +
1 file changed, 5 insertions(+), 8 deletions(-)
diff --git a/drivers/crypto/hisilicon/hpre/hpre_crypto.c
b/drivers/cr
From: Meng Yu
Using 'g' not equal to 2 in dh algorithm may cause an error like this:
arm-smmu-v3 arm-smmu-v3.1.auto: event 0x10 received:
dh: Party A: generate public key test failed. err -22
11375.065672] dh alg: dh: test failed on vector 1, err=-22
arm-smmu-v3 arm-smmu-v3.1.auto: 0x79
From: Colin Ian King
There is a statement that is indented by one whitespace too deeply,
fix this by removing the whitespace.
Signed-off-by: Colin Ian King
---
drivers/crypto/chelsio/chcr_core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/chelsio/chcr_cor
On Fri, Sep 18, 2020 at 04:42:07PM -0400, Theodore Y. Ts'o wrote:
>
> We're currently not bothering to deal with Endian conversions with the counter
Endianness conversion for the counter isn't needed because the implementation
only treats it as words, not as bytes.
(Exception: the counter does ge
On Tue, Sep 15, 2020 at 09:50:13PM -0700, Eric Biggers wrote:
> From: Eric Biggers
>
> On big endian CPUs, the ChaCha20-based CRNG is using the wrong
> endianness for the ChaCha20 constants.
>
> This doesn't matter cryptographically, but technically it means it's not
> ChaCha20 anymore. Fix it
On Fri, 18 Sep 2020 at 22:08, Nick Desaulniers wrote:
>
> On Wed, Sep 16, 2020 at 11:08 PM Ard Biesheuvel wrote:
> >
> > On Thu, 17 Sep 2020 at 03:53, Nick Desaulniers
> > wrote:
> > >
> > > One thing I noticed was that if I grep for `adrl` with all of the
> > > above applied within arch/arm, I
On Thu, 2020-09-17 at 18:58 +0530, Srujana Challa wrote:
> Add support for the cryptographic acceleration unit (CPT) on
>
> OcteonTX2 CN96XX SoC.
>
>
>
> Signed-off-by: Suheil Chandran
>
> Signed-off-by: Lukas Bartosik
>
> Signed-off-by: Srujana Challa
>
> ---
[...]
> 15 files changed,
On Thu, 2020-09-17 at 18:58 +0530, Srujana Challa wrote:
>
>
> +int rvu_mbox_handler_nix_inline_ipsec_lf_cfg(struct rvu *rvu,
>
> + struct nix_inline_ipsec_lf_cfg *req, struct msg_rsp
>
Can you do something about this code alignment ?
checkpatch outputs:
--
On Thu, 2020-09-17 at 18:58 +0530, Srujana Challa wrote:
> The following series adds support for Marvell Cryptographic
> Acceleration
> Unit(CPT) on OcteonTX2 CN96XX SoC.
> This series is tested with CRYPTO_EXTRA_TESTS enabled and
> CRYPTO_DISABLE_TESTS disabled.
>
I am with Jakub on this one, 10
On 9/18/20 2:47 PM, Herbert Xu wrote:
On Thu, Sep 03, 2020 at 09:12:39PM +0800, Tianjia Zhang wrote:
Some asymmetric algorithms will get different ciphertext after
each encryption, such as SM2, and let testmgr support the testing
of such algorithms.
In struct akcipher_testvec, set c and c_si
Hi "Stephan,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on char-misc/char-misc-testing]
[also build test ERROR on cryptodev/master crypto/master v5.9-rc5 next-20200918]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submi
> Subject: [EXT] Re: [PATCH v3,net-next,0/4] Add Support for Marvell OcteonTX2
> Cryptographic
>
> External Email
>
> --
> On Thu, 17 Sep 2020 18:58:31 +0530 Srujana Challa wrote:
> > The following series adds support for Marvell
In order to improve NUMA-locality when serving getrandom(2) requests,
allocate one DRNG instance per node.
The DRNG instance that is present right from the start of the kernel is
reused as the first per-NUMA-node DRNG. For all remaining online NUMA
nodes a new DRNG instance is allocated.
During b
Hi,
The following patch set provides a different approach to /dev/random which
is called Linux Random Number Generator (LRNG) to collect entropy within
the Linux kernel.
The following advantages compared to the existing /dev/random
implementation are present:
* Sole use of crypto for data proces
This patch allows several DRBG functions to be called by the LRNG kernel
code paths outside the drbg.c file.
CC: "Eric W. Biederman"
CC: "Alexander E. Patrakov"
CC: "Ahmed S. Darwish"
CC: "Theodore Y. Ts'o"
CC: Willy Tarreau
CC: Matthew Garrett
CC: Vito Caputo
CC: Andreas Dilger
CC: Jan Ka
The LRNG switchable DRNG support also allows the replacement of the hash
implementation used as conditioning component. The common generic hash
support code provides the required callbacks using the synchronous hash
implementations of the kernel crypto API.
All synchronous hash implementations sup
The DRNG switch support allows replacing the DRNG mechanism of the
LRNG. The switching support rests on the interface definition of
include/linux/lrng.h. A new DRNG is implemented by filling in the
interface defined in this header file.
In addition to the DRNG, the extension also has to provide a
The Jitter RNG fast noise source implemented as part of the kernel
crypto API is queried for 256 bits of entropy at the time the seed
buffer managed by the LRNG is about to be filled.
CC: "Eric W. Biederman"
CC: "Alexander E. Patrakov"
CC: "Ahmed S. Darwish"
CC: "Theodore Y. Ts'o"
CC: Willy Ta
Implement health tests for LRNG's slow noise sources as mandated by
SP-800-90B The file contains the following health tests:
- stuck test: The stuck test calculates the first, second and third
discrete derivative of the time stamp to be processed by the hash
for the per-CPU entropy pool. Only
To support the LRNG operation which uses the Jitter RNG separately
from the kernel crypto API, at a time where potentially the regular
memory management is not yet initialized, the Jitter RNG needs to
provide a state whose memory is defined at compile time. As only once
instance will ever be needed
The test interface allows a privileged process to capture the raw
unconditioned noise that is collected by the LRNG for statistical
analysis. Such testing allows the analysis how much entropy
the interrupt noise source provides on a given platform.
Extracted noise data is not used to seed the LRNG.
Parts of the LRNG are already covered by self-tests, including:
* Self-test of SP800-90A DRBG provided by the Linux kernel crypto API.
* Self-test of the PRNG provided by the Linux kernel crypto API.
* Raw noise source data testing including SP800-90B compliant
tests when enabling CONFIG_LRNG_
In an effort to provide a flexible implementation for a random number
generator that also delivers entropy during early boot time, allows
replacement of the deterministic random number generation mechanism,
implement the various components in separate code for easier
maintenance, and provide compli
The LRNG sysctl interface provides the same controls as the existing
/dev/random implementation. These sysctls behave identically and are
implemented identically. The goal is to allow a possible merge of the
existing /dev/random implementation with this implementation which
implies that this patch
Using the LRNG switchable DRNG support, the SP800-90A DRBG extension is
implemented.
The DRBG uses the kernel crypto API DRBG implementation. In addition, it
uses the kernel crypto API SHASH support to provide the hashing
operation.
The DRBG supports the choice of either a CTR DRBG using AES-256,
Add runtime-pluggable support for all PRNGs that are accessible via
the kernel crypto API, including hardware PRNGs. The PRNG is selected
with the module parameter drng_name where the name must be one that the
kernel crypto API can resolve into an RNG.
This allows using of the kernel crypto API PR
Yes, 'u64' is redundant, I will resend one!
Thank you!
On 2020/9/18 15:11, Herbert Xu wrote:
On Thu, Sep 10, 2020 at 07:25:22PM +0800, Meng Yu wrote:
diff --git a/drivers/crypto/hisilicon/hpre/hpre_crypto.c
b/drivers/crypto/hisilicon/hpre/hpre_crypto.c
index 0cbe99a1
On Fri, Sep 18, 2020 at 10:06:58AM +0200, LABBE Corentin wrote:
>
> But I think only me will see it and since I already have this on my TODO
> list, I dont see any interest to leave it failing.
> Furthermore, having a clean BE boot will permit to enable BE boots for thoses
> SoCs on kernelCI.
I'
> -Original Message-
> From: Herbert Xu
> Sent: Friday, September 18, 2020 10:01 AM
> To: Van Leeuwen, Pascal
> Cc: linux-crypto@vger.kernel.org; antoine.ten...@bootlin.com;
> da...@davemloft.net; Ard Biesheuvel
> Subject: Re: [PATCH] crypto: inside-secure - Fix corruption on not fully
On Fri, Sep 18, 2020 at 05:31:28PM +1000, Herbert Xu wrote:
> On Thu, Sep 17, 2020 at 06:35:55PM +, Corentin Labbe wrote:
> > Ciphers produce invalid results on BE.
> > Key and IV need to be written in LE.
> > Furthermore, the non-optimized function is too complicated to convert,
> > let's simp
On Fri, Sep 18, 2020 at 05:50:36PM +1000, Herbert Xu wrote:
> On Fri, Sep 18, 2020 at 09:49:11AM +0200, Greg KH wrote:
> >
> > Ok, I'll go revert these.
>
> Thanks!
>
> > > As the driver has been converted over to the lib arc4 API, it
> > > does not need to select CRYPTO at all.
> >
> > Is it co
On Fri, Sep 18, 2020 at 07:42:35AM +, Van Leeuwen, Pascal wrote:
>
> Actually, that is what we did as a _quick hack_ initially, but:
>
> First of all, it's not only about the L1 cacheline size. It's about the worst
> case cache
> line size in the path all the way from the CPU to the actual me
On Fri, Sep 18, 2020 at 03:41:34PM +1000, Herbert Xu wrote:
> On Fri, Sep 18, 2020 at 03:21:27PM +1000, Stephen Rothwell wrote:
> > Hi all,
> >
> > Today's linux-next merge of the staging tree got a conflict in:
> >
> > drivers/staging/rtl8192e/Kconfig
> >
> > between commit:
> >
> > 054694
On Fri, Sep 18, 2020 at 09:49:11AM +0200, Greg KH wrote:
>
> Ok, I'll go revert these.
Thanks!
> > As the driver has been converted over to the lib arc4 API, it
> > does not need to select CRYPTO at all.
>
> Is it converted in your tree? If so, have a branch/tag I can pull in to
> prevent merge
> -Original Message-
> From: Herbert Xu
> Sent: Friday, September 18, 2020 8:58 AM
> To: Van Leeuwen, Pascal
> Cc: linux-crypto@vger.kernel.org; antoine.ten...@bootlin.com;
> da...@davemloft.net
> Subject: Re: [PATCH] crypto: inside-secure - Fix corruption on not fully
> coherent syste
On Thu, Sep 17, 2020 at 06:35:55PM +, Corentin Labbe wrote:
> Ciphers produce invalid results on BE.
> Key and IV need to be written in LE.
> Furthermore, the non-optimized function is too complicated to convert,
> let's simply fallback on BE for the moment.
>
> Fixes: 6298e948215f2 ("crypto:
On Thu, Sep 10, 2020 at 09:29:16PM +0200, Krzysztof Kozlowski wrote:
> Fix kerneldoc warnings like:
>
> drivers/crypto/caam/caamalg_qi2.c:73: warning: cannot understand function
> prototype: 'struct caam_ctx'
> drivers/crypto/caam/caamalg_qi2.c:2962: warning: cannot understand function
> pro
On Fri, Sep 11, 2020 at 05:11:03PM +0300, Ard Biesheuvel wrote:
> We have a few interesting pieces in our cipher museum, which are never
> used internally, and were only ever provided as generic C implementations.
>
> Unfortunately, we cannot simply remove this code, as we cannot be sure
> that it
On Fri, Sep 11, 2020 at 09:46:39AM +0200, Pascal van Leeuwen wrote:
> This patch adds support for EIP197 instances that include the output
> classifier (OCE) option, as used by one of our biggest customers.
> The OCE normally requires initialization and dedicated firmware, but
> for the simple oper
On Wed, Sep 09, 2020 at 12:45:28PM +0300, Dan Carpenter wrote:
> The pm_runtime_get_sync() function returns either 0 or 1 on success but
> this code treats a return of 1 as a failure.
>
> Fixes: 7694b6ca649f ("crypto: sa2ul - Add crypto driver")
> Signed-off-by: Dan Carpenter
> ---
> drivers/cry
On Wed, Sep 09, 2020 at 11:59:38AM +0100, Giovanni Cabiddu wrote:
> Resending patches 4 and 5 from the series "vfio/pci: add denylist and
> disable qat" that didn't get apply.
>
> This set replaces the device IDs defined in the qat drivers with the ones
> in linux/pci_ids.h and replaces the custom
On Thu, Sep 10, 2020 at 07:56:38PM +0800, Longfang Liu wrote:
> In order to pass kernel crypto test, the ACC module parameter
> pf_q_num needs to be set to an integer greater than 1,
> and then fixed two bugs.
>
> Longfang Liu (5):
> crypto: hisilicon - update mininum queue
> crypto: hisilicon
On Mon, Sep 07, 2020 at 10:56:10AM +0300, Tero Kristo wrote:
> Convert the omap-sham driver to use crypto engine for queue handling,
> instead of using local implementation.
>
> Signed-off-by: Tero Kristo
> ---
> drivers/crypto/omap-sham.c | 186 -
> 1 file ch
On Mon, Sep 07, 2020 at 10:56:24AM +0300, Tero Kristo wrote:
> Running export/import for hashes in peculiar order (mostly done by
> openssl) can mess up the internal book keeping of the OMAP SHA core.
> Fix by forcibly writing the correct DIGCNT back to hardware. This issue
> was noticed while tran
On Tue, Sep 08, 2020 at 08:10:45AM +0200, Pascal van Leeuwen wrote:
> On systems with coherence issues, packet processed could succeed while
> it should have failed, e.g. because of an authentication fail.
> This is because the driver would read stale status information that had
> all error bits in
On Mon, Sep 07, 2020 at 04:21:52PM +0800, Yang Shen wrote:
> This patchset make some clean up:
> patch 1:remove useless parameters
> patch 4:replace 'sprintf' with 'scnprintf'
> patch 7:fix static check warning
> and the rest patch fix some coding style
>
> v2:
> - remove the return check of 'scnp
Instead of using an hardcoded value, let's use a defined value for
SS_START.
Signed-off-by: Corentin Labbe
---
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c | 2 +-
drivers/crypto/allwinner/sun8i-ss/sun8i-ss.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers
Error registers are different across SoCs.
This patch handle those difference.
Signed-off-by: Corentin Labbe
---
.../crypto/allwinner/sun8i-ce/sun8i-ce-core.c | 62 ---
drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h | 8 +++
2 files changed, 62 insertions(+), 8 deletions(-)
diff
This patch had support for the TRNG present in the CE.
Note that according to the algorithm ID, 2 version of the TRNG exists,
the first present in H3/H5/R40/A64 and the second present in H6.
This patch adds support for both, but only the second is working
reliabily according to rngtest.
Signed-off
Hello
The main goal of this serie is to add support for TRNG, PRNG and hashes
to the sun8i-ss/sun8i-ce driver.
The whole serie is tested with CRYPTO_EXTRA_TESTS enabled and loading
tcrypt.
The PRNG and TRNG are tested with rngtest.
Both LE and BE kernel are tested.
This serie was tested on:
- sun
Instead of storing IV data in the channel context, store them in the
request context.
Storing them in the channel structure was conceptualy wrong since they
are per request related.
Signed-off-by: Corentin Labbe
---
.../allwinner/sun8i-ce/sun8i-ce-cipher.c | 27 +--
drivers/
Hash algorithms will need also a spetial t_dlen handling, but since the
meaning will be different, rename the current flag to specify it apply
only on ciphers algorithms.
Signed-off-by: Corentin Labbe
---
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-cipher.c | 2 +-
drivers/crypto/allwinner/sun8i-
This patch split the do_one_request into three.
Prepare will handle all DMA mapping and initialisation of the task
structure.
Unprepare will clean all DMA mapping.
And the do_one_request will be limited to just executing the task.
Signed-off-by: Corentin Labbe
---
.../allwinner/sun8i-ce/sun8i-ce
This patch fixes the warning:
warning: comparison of integer expressions of different signedness: 'int' and
'long unsigned int' [-Wsign-compare]
Signed-off-by: Corentin Labbe
---
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff
This patch adds a new stat_bytes counter in the sun8i-ce debugfs.
Signed-off-by: Corentin Labbe
---
drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h
b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h
inde
The SS support multiples hash algorithms, this patch adds support for
MD5, SHA1, SHA224 and SHA256.
Signed-off-by: Corentin Labbe
---
drivers/crypto/allwinner/Kconfig | 9 +
drivers/crypto/allwinner/sun8i-ss/Makefile| 1 +
.../crypto/allwinner/sun8i-ss/sun8i-ss-core.c | 155
This patch fixes the warning:
warning: comparison of integer expressions of different signedness: 'int' and
'long unsigned int' [-Wsign-compare]
Signed-off-by: Corentin Labbe
---
drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff
t_common_ctl is LE32 so we need to convert its value before using it.
This value is only used on H6 (ignored on other SoCs) and not handling
the endianness cause failure on xRNG/hashes operations on H6 when running BE.
Fixes: 06f751b61329 ("crypto: allwinner - Add sun8i-ce Crypto Engine")
Signed-o
The CE support multiples hash algorithms, this patch adds support for
MD5, SHA1, SHA224, SHA256, SHA384 and SHA512.
Signed-off-by: Corentin Labbe
---
drivers/crypto/allwinner/Kconfig | 10 +
drivers/crypto/allwinner/sun8i-ce/Makefile| 1 +
.../crypto/allwinner/sun8i-ce/sun8i-
This patch adds some comment on structures used by sun8i-ss.
Signed-off-by: Corentin Labbe
---
drivers/crypto/allwinner/sun8i-ss/sun8i-ss.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/crypto/allwinner/sun8i-ss/sun8i-ss.h
b/drivers/crypto/allwinner/sun8i-ss/sun8i-ss.h
index da7
This patch reworks the way debug info are printed.
Instead of printing raw numbers, let's add a bit of context.
Signed-off-by: Corentin Labbe
---
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-core.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/crypto/allwinner/s
This patch had support for the PRNG present in the CE.
The output was tested with rngtest without any failure.
Signed-off-by: Corentin Labbe
---
drivers/crypto/allwinner/Kconfig | 8 +
drivers/crypto/allwinner/sun8i-ce/Makefile| 1 +
.../crypto/allwinner/sun8i-ce/sun8i-ce-co
This fixes a trivial typo.
Signed-off-by: Corentin Labbe
---
drivers/crypto/allwinner/sun8i-ss/sun8i-ss.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/allwinner/sun8i-ss/sun8i-ss.h
b/drivers/crypto/allwinner/sun8i-ss/sun8i-ss.h
index 377ea7acb54d..da71d8059
This patch had support for the PRNG present in the SS.
The output was tested with rngtest without any failure.
Signed-off-by: Corentin Labbe
---
drivers/crypto/allwinner/Kconfig | 8 +
drivers/crypto/allwinner/sun8i-ss/Makefile| 1 +
.../crypto/allwinner/sun8i-ss/sun8i-ss-co
On Thu, Sep 10, 2020 at 07:25:22PM +0800, Meng Yu wrote:
>
> diff --git a/drivers/crypto/hisilicon/hpre/hpre_crypto.c
> b/drivers/crypto/hisilicon/hpre/hpre_crypto.c
> index 0cbe99a1..2d91593 100644
> --- a/drivers/crypto/hisilicon/hpre/hpre_crypto.c
> +++ b/drivers/crypto/hisilicon/hpre/hpre_cryp
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