On Sat, Jul 18, 2020 at 04:25:29PM +0300, Ard Biesheuvel wrote:
> On Sat, 18 Jul 2020 at 12:43, Sven Auhagen wrote:
> >
> > Balance the irqs of the inside secure driver over all
> > available cpus.
> > Currently all interrupts are handled by the first CPU.
> >
> > From my testing with IPSec AES-GC
On Sat, 18 Jul 2020 at 12:43, Sven Auhagen wrote:
>
> Balance the irqs of the inside secure driver over all
> available cpus.
> Currently all interrupts are handled by the first CPU.
>
> From my testing with IPSec AES-GCM 256
> on my MCbin with 4 Cores I get a 50% speed increase:
>
> Before the pa
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.
Deterministic algorithm:
For each file:
If not .svg:
For each line:
If doesn't contain `\bxmlns\b`:
For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
Balance the irqs of the marvell cesa driver over all
available cpus.
Currently all interrupts are handled by the first CPU.
>From my testing with IPSec AES 256 SHA256
on my clearfog base with 2 Cores I get a 2x speed increase:
Before the patch: 26.74 Kpps
With the patch: 56.11 Kpps
Signed-off-by
Balance the irqs of the inside secure driver over all
available cpus.
Currently all interrupts are handled by the first CPU.
>From my testing with IPSec AES-GCM 256
on my MCbin with 4 Cores I get a 50% speed increase:
Before the patch: 99.73 Kpps
With the patch: 151.25 Kpps
Signed-off-by: Sven A
On Fri, 3 Jul 2020 at 02:04, Ard Biesheuvel wrote:
>
> On Thu, 2 Jul 2020 at 20:21, Ard Biesheuvel wrote:
> >
> > On Thu, 2 Jul 2020 at 19:50, Eric Biggers wrote:
> > >
> > > [+linux-wireless, Marcel Holtmann, and Denis Kenzior]
> > >
> > > On Thu, Jul 02, 2020 at 12:19:44PM +0200, Ard Biesheuve
