From: Eric Biggers
Overly-generic names can cause problems like naming collisions,
confusing crash reports, and reduced grep-ability. E.g. see
commit d099ea6e6fde ("crypto - Avoid free() namespace collision").
Clean this up for the xts template by prefixing the names with "xts_".
(I didn't use
From: Eric Biggers
Overly-generic names can cause problems like naming collisions,
confusing crash reports, and reduced grep-ability. E.g. see
commit d099ea6e6fde ("crypto - Avoid free() namespace collision").
Clean this up for the lrw template by prefixing the names with "lrw_".
(I didn't use
On Fri, Jul 10, 2020 at 10:10:34AM -0600, Alex Williamson wrote:
> On Fri, 10 Jul 2020 10:44:33 -0500
> Bjorn Helgaas wrote:
>
> > On Fri, Jul 10, 2020 at 10:37:45AM -0500, Bjorn Helgaas wrote:
> > > On Fri, Jul 10, 2020 at 04:08:19PM +0100, Giovanni Cabiddu wrote:
> > > > On Wed, Jul 01, 2020
On Fri, Jul 10, 2020 at 04:48:07PM +0100, Christoph Hellwig wrote:
> On Wed, Jul 01, 2020 at 01:42:09PM +0100, Christoph Hellwig wrote:
> > On Wed, Jul 01, 2020 at 12:02:57PM +0100, Giovanni Cabiddu wrote:
> > > This patchset defines a blocklist of devices in the vfio-pci module and
> > > adds
> >
On Fri, 10 Jul 2020 10:44:33 -0500
Bjorn Helgaas wrote:
> On Fri, Jul 10, 2020 at 10:37:45AM -0500, Bjorn Helgaas wrote:
> > On Fri, Jul 10, 2020 at 04:08:19PM +0100, Giovanni Cabiddu wrote:
> > > On Wed, Jul 01, 2020 at 04:28:12PM -0500, Bjorn Helgaas wrote:
> > > > On Wed, Jul 01, 2020 at 1
On Wed, Jul 01, 2020 at 01:42:09PM +0100, Christoph Hellwig wrote:
> On Wed, Jul 01, 2020 at 12:02:57PM +0100, Giovanni Cabiddu wrote:
> > This patchset defines a blocklist of devices in the vfio-pci module and adds
> > the current generation of Intel(R) QuickAssist devices to it as they are
> > no
On Fri, Jul 10, 2020 at 10:37:45AM -0500, Bjorn Helgaas wrote:
> On Fri, Jul 10, 2020 at 04:08:19PM +0100, Giovanni Cabiddu wrote:
> > On Wed, Jul 01, 2020 at 04:28:12PM -0500, Bjorn Helgaas wrote:
> > > On Wed, Jul 01, 2020 at 12:03:00PM +0100, Giovanni Cabiddu wrote:
> > > > The current generatio
On Fri, Jul 10, 2020 at 04:08:19PM +0100, Giovanni Cabiddu wrote:
> On Wed, Jul 01, 2020 at 04:28:12PM -0500, Bjorn Helgaas wrote:
> > On Wed, Jul 01, 2020 at 12:03:00PM +0100, Giovanni Cabiddu wrote:
> > > The current generation of Intel® QuickAssist Technology devices
> > > are not designed to ru
Am Freitag, 10. Juli 2020, 16:42:39 CEST schrieb Ard Biesheuvel:
Hi Ard,
> On Fri, 10 Jul 2020 at 13:16, Stephan Müller wrote:
> > Add mpi_sub_ui() based on Gnu PG mpz_sub_ui() from mpz/aors_ui.h
> > adapting the code to the kernel's structures and coding style and also
> > removing the defines
On Wed, Jul 01, 2020 at 04:28:12PM -0500, Bjorn Helgaas wrote:
> On Wed, Jul 01, 2020 at 12:03:00PM +0100, Giovanni Cabiddu wrote:
> > The current generation of Intel® QuickAssist Technology devices
> > are not designed to run in an untrusted environment because of the
> > following issues reported
On Fri, 10 Jul 2020 at 13:16, Stephan Müller wrote:
>
> Add mpi_sub_ui() based on Gnu PG mpz_sub_ui() from mpz/aors_ui.h
> adapting the code to the kernel's structures and coding style and also
> removing the defines used to produce mpz_sub_ui() and mpz_add_ui()
> from the same code.
>
Isn't GnuP
Hi, Tianjia.
On Thu, Jul 09, 2020 at 04:40:09PM +0800, Tianjia Zhang wrote:
> Expand the mpi library based on libgcrypt, and the ECC algorithm of
> mpi based on libgcrypt requires these functions.
> Some other algorithms will be developed based on mpi ecc, such as SM2.
>
> Signed-off-by: Tianjia
SP800-56A rev3 section 5.7.1.1 step 2 mandates that the validity of the
calculated shared secret is verified before the data is returned to the
caller. This patch adds the validation check.
Signed-off-by: Marcelo Henrique Cerri
Signed-off-by: Stephan Mueller
---
crypto/dh.c | 29 +++
Hi,
The patch set adds the shared secret validation as defined by
SP800-56A rev 3. For ECDH this only implies that the validation
of the shared secret is moved before the shared secret is
returned to the caller.
For DH, the validation is required to be performed against the prime
of the domain pa
>From 5385865b3f44d331f91c6786a2e7f4e2fb4d8cb2 Mon Sep 17 00:00:00 2001
From: Stephan Mueller
Date: Thu, 11 Jun 2020 08:12:54 +0200
Subject:
SP800-56A rev3 section 5.7.1.2 step 2 mandates that the validity of the
calculated shared secret is verified before the data is returned to the
caller. Thu
Add mpi_sub_ui() based on Gnu PG mpz_sub_ui() from mpz/aors_ui.h
adapting the code to the kernel's structures and coding style and also
removing the defines used to produce mpz_sub_ui() and mpz_add_ui()
from the same code.
Signed-off-by: Marcelo Henrique Cerri
Signed-off-by: Stephan Mueller
---
[ Please CC me I am not subscribed to this ML ]
[ Original patch from Arnd (see [0]) ]
Hi,
as reported in [1] this is the last patch we "ClangBuiltLinux folks"
need to be full compliant with LLVM_IAS=1 (for example with Linux
v5.8-rc4).
These two commits entered recently cryptodev-2.6.git:
comm
On Thu, Jul 9, 2020 at 2:56 PM Herbert Xu wrote:
>
> On Fri, Jul 03, 2020 at 04:32:06PM +0200, Sedat Dilek wrote:
> > When building with LLVM_IAS=1 means using Clang's Integrated Assembly (IAS)
> > from LLVM/Clang >= v10.0.1-rc1+ instead of GNU/as from GNU/binutils
> > I see the following breakage
Initialize current queue number as HPRE_PF_DEF_Q_NUM, or it is zero
and we can't set its value by "current_q_write".
Signed-off-by: Meng Yu
Reviewed-by: Zaibo Xu
Reviewed-by: Hui Tang
---
drivers/crypto/hisilicon/hpre/hpre_main.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cryp
From: Hui Tang
for Hi1620 hardware, we should disable these hardware flr:
1. BME_FLR - bit 7,
2. PM_FLR - bit 11,
3. SRIOV_FLR - bit 12,
Or HPRE may goto D3 state, when we bind and unbind HPRE quickly,
as it does FLR triggered by BME/PM/SRIOV.
Fixes: c8b4b477079d("crypto: hisilicon - add HiSilic
Bugfix: crypto: hisilicon/hpre - modify the macros, add a switch in
sriov_configure, unified debugfs interface, and disable
hardware FLR.
Hui Tang (2):
crypto: hisilicon/hpre - HPRE_OVERTIME_THRHLD can be written by
debugfs
crypto: hisilicon/hpre - disable FLR triggered by hardware
Update debugfs interface parameters, and adjust the
processing logic inside the corresponding function.
Fixes: 848974151618("crypto: hisilicon - Add debugfs for HPRE")
Signed-off-by: Meng Yu
Reviewed-by: Zaibo Xu
---
drivers/crypto/hisilicon/hpre/hpre_main.c | 59 ++-
If CONFIG_PCI_IOV is not enabled, we can not use "sriov_configure".
Fixes: 5ec302a364bf("crypto: hisilicon - add SRIOV support for HPRE")
Signed-off-by: Meng Yu
Reviewed-by: Zaibo Xu
Reviewed-by: Shukun Tan
---
drivers/crypto/hisilicon/hpre/hpre_main.c | 3 ++-
1 file changed, 2 insertions(+),
From: Hui Tang
Registers in "hpre_dfx_files" can only be cleaned to zero but
HPRE_OVERTIME_THRHLD, which can be written as any number.
Fixes: 64a6301ebee7("crypto: hisilicon/hpre - add debugfs for ...")
Signed-off-by: Hui Tang
Signed-off-by: Meng Yu
Reviewed-by: Zaibo Xu
Reviewed-by: Zhou Wan
1. Bit 1 to bit 5 are NFE, not CE.
2. Macro 'HPRE_VF_NUM' is defined in 'qm.h', so delete it here.
3. Delete multiple blank lines.
4. Adjust format alignment.
Signed-off-by: Meng Yu
Reviewed-by: Zaibo Xu
Reviewed-by: Longfang Liu
---
drivers/crypto/hisilicon/hpre/hpre_main.c | 12 +---
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