Even though the sahara driver implements asynchronous versions of
ecb(aes) and cbc(aes), the fallbacks it allocates are required to be
synchronous. Given that SIMD based software implementations are usually
asynchronous as well, even though they rarely complete asynchronously
(this typically only h
Even though the chelsio driver implements asynchronous versions of
cbc(aes) and xts(aes), the fallbacks it allocates are required to be
synchronous. Given that SIMD based software implementations are usually
asynchronous as well, even though they rarely complete asynchronously
(this typically only
The Mediatek accelerator driver calls into a dynamically allocated
skcipher of the ctr(aes) variety to perform GCM key derivation, which
involves AES encryption of a single block consisting of NUL bytes.
There is no point in using the skcipher API for this, so use the AES
library interface instead
Even though the mxs-dcp driver implements asynchronous versions of
ecb(aes) and cbc(aes), the fallbacks it allocates are required to be
synchronous. Given that SIMD based software implementations are usually
asynchronous as well, even though they rarely complete asynchronously
(this typically only
Even though the picoxcell driver implements asynchronous versions of
ecb(aes) and cbc(aes), the fallbacks it allocates are required to be
synchronous. Given that SIMD based software implementations are usually
asynchronous as well, even though they rarely complete asynchronously
(this typically onl
Even though the qce driver implements asynchronous versions of ecb(aes),
cbc(aes)and xts(aes), the fallbacks it allocates are required to be
synchronous. Given that SIMD based software implementations are usually
asynchronous as well, even though they rarely complete asynchronously
(this typically
Even though the sun8i-ce driver implements asynchronous versions of
ecb(aes) and cbc(aes), the fallbacks it allocates are required to be
synchronous. Given that SIMD based software implementations are usually
asynchronous as well, even though they rarely complete asynchronously
(this typically only
Even though the sun8i-ss driver implements asynchronous versions of
ecb(aes) and cbc(aes), the fallbacks it allocates are required to be
synchronous. Given that SIMD based software implementations are usually
asynchronous as well, even though they rarely complete asynchronously
(this typically only
Even though the ccp driver implements an asynchronous version of xts(aes),
the fallback it allocates is required to be synchronous. Given that SIMD
based software implementations are usually asynchronous as well, even
though they rarely complete asynchronously (this typically only happens
in cases
The AmLogic GXL crypto accelerator driver is built into the kernel if
ARCH_MESON is set. However, given the single image policy of arm64, its
defconfig enables all platforms by default, and so ARCH_MESON is usually
enabled.
This means that the AmLogic driver causes the arm64 defconfig build to
pul
Even though the sun4i driver implements asynchronous versions of ecb(aes)
and cbc(aes), the fallbacks it allocates are required to be synchronous.
Given that SIMD based software implementations are usually asynchronous
as well, even though they rarely complete asynchronously (this typically
only ha
The drivers for crypto accelerators in drivers/crypto all implement skciphers
of an asynchronous nature, given that they are backed by hardware DMA that
completes asynchronously wrt the execution flow.
However, in many cases, any fallbacks they allocate are limited to the
synchronous variety, whic
Even though the amlogic-gxl driver implements asynchronous versions of
ecb(aes) and cbc(aes), the fallbacks it allocates are required to be
synchronous. Given that SIMD based software implementations are usually
asynchronous as well, even though they rarely complete asynchronously
(this typically o
Even though the omap-aes driver implements asynchronous versions of
ecb(aes), cbc(aes) and ctr(aes), the fallbacks it allocates are required
to be synchronous. Given that SIMD based software implementations are
usually asynchronous as well, even though they rarely complete
asynchronously (this typi
There are multiple things in this file that requires kernel.h but
it's only included through other header files indirectly. This
patch adds a direct inclusion as those indirect inclusions may go
away at any point.
Signed-off-by: Herbert Xu
diff --git a/drivers/char/hw_random/ba431-rng.c
b/driv
Update debugfs interface parameters, and adjust the
processing logic inside the corresponding function
Signed-off-by: Longfang Liu
---
drivers/crypto/hisilicon/sec2/sec_main.c | 54
1 file changed, 27 insertions(+), 27 deletions(-)
diff --git a/drivers/crypto/hi
From: Kai Ye
SEC debug registers aren't cleared even if its driver is removed,
so add a clearing operation in driver removing.
Signed-off-by: Kai Ye
Reviewed-by: Longfang Liu
---
drivers/crypto/hisilicon/sec2/sec_main.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/crypto
Updates the initialization and reset of SEC driver's
register operation.
Signed-off-by: Longfang Liu
---
drivers/crypto/hisilicon/qm.h| 1 +
drivers/crypto/hisilicon/sec2/sec_main.c | 55
2 files changed, 29 insertions(+), 27 deletions(-)
diff --git
Modify some log output interfaces and
update author information
Signed-off-by: Longfang Liu
---
drivers/crypto/hisilicon/sec2/sec_main.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/crypto/hisilicon/sec2/sec_main.c
b/drivers/crypto/hisilicon/sec2/sec_main
From: Kai Ye
As before, if a SEC queue is at the 'fake busy' status,
the request with a 'fake busy' flag will be sent into hardware
and the sending function returns busy. After the request is
finished, SEC driver's call back will identify the 'fake busy' flag,
and notifies the user that hardware
Fix some SEC driver bugs and modify some coding styles
Changes v1 -> v2:
- Apply MAY_BACKLOG.
Kai Ye (2):
crypto: hisilicon/sec2 - clear SEC debug regs
crypto:hisilicon/sec2 - update busy processing logic
Longfang Liu (3):
crypto: hisilicon/sec2 - update SEC initialization and rese
On Mon, Jul 06, 2020 at 12:07:17PM -0700, Eric Biggers wrote:
>
> This changes chacha_state to be a pointer, which breaks clearing the state
> because that uses sizeof(chacha_state):
>
> memzero_explicit(chacha_state, sizeof(chacha_state));
>
> It would need to be changed to use CHACHA_BLOC
--
Dear Friend,
I'm Mr. Scott Donald a Successful business Man dealing with
Exportation, I got your mail contact through search to let you know my
Ugly Situation Am a dying Man here in Los Angeles California Hospital
Bed in (USA), I Lost my Wife and my only Daughter for Covid-19 I'm
dying with sa
On Tue, Jun 30, 2020 at 02:18:59PM +0200, Ard Biesheuvel wrote:
> Even though the sun8i-ce driver implements asynchronous versions of
> ecb(aes) and cbc(aes), the fallbacks it allocates are required to be
> synchronous. Given that SIMD based software implementations are usually
> asynchronous as we
On Tue, Jun 30, 2020 at 02:19:00PM +0200, Ard Biesheuvel wrote:
> Even though the sun8i-ss driver implements asynchronous versions of
> ecb(aes) and cbc(aes), the fallbacks it allocates are required to be
> synchronous. Given that SIMD based software implementations are usually
> asynchronous as we
On Mon, Jul 06, 2020 at 11:37:34PM +1000, Herbert Xu wrote:
> diff --git a/lib/crypto/chacha20poly1305.c b/lib/crypto/chacha20poly1305.c
> index ad0699ce702f9..1d7bb0b91b83c 100644
> --- a/lib/crypto/chacha20poly1305.c
> +++ b/lib/crypto/chacha20poly1305.c
> @@ -94,7 +94,7 @@ void chacha20poly1305_
On Wed, Jul 01, 2020 at 03:59:10AM -0400, Mikulas Patocka wrote:
> Thanks for cleaning this up.
>
> Mikulas
Do you have any real comments on this?
Are the usage restrictions okay for dm-crypt?
- Eric
On Tue, Jun 30, 2020 at 02:18:56PM +0200, Ard Biesheuvel wrote:
> Even though the amlogic-gxl driver implements asynchronous versions of
> ecb(aes) and cbc(aes), the fallbacks it allocates are required to be
> synchronous. Given that SIMD based software implementations are usually
> asynchronous as
On Tue, Jun 30, 2020 at 02:18:55PM +0200, Ard Biesheuvel wrote:
> The AmLogic GXL crypto accelerator driver is built into the kernel if
> ARCH_MESON is set. However, given the single image policy of arm64, its
> defconfig enables all platforms by default, and so ARCH_MESON is usually
> enabled.
>
Please contact Email:( fedexcommonwealt...@yahoo.com ) For your donation
of $800,000.00 by CommonWealth Of Nation
---Universidad de Camaguey "Ignacio Agramonte Loynaz", Cuba
http://www.reduc.edu.cu/
On Tue, Jun 30, 2020 at 02:18:58PM +0200, Ard Biesheuvel wrote:
> Even though the sun4i driver implements asynchronous versions of ecb(aes)
> and cbc(aes), the fallbacks it allocates are required to be synchronous.
> Given that SIMD based software implementations are usually asynchronous
> as well,
On Tue, Jun 30, 2020 at 02:19:04PM +0200, Ard Biesheuvel wrote:
> Even though the picoxcell driver implements asynchronous versions of
> ecb(aes) and cbc(aes), the fallbacks it allocates are required to be
> synchronous. Given that SIMD based software implementations are usually
> asynchronous as w
On Sun, 5 Jul 2020 at 22:11, Horia Geantă wrote:
>
> On 7/2/2020 7:36 AM, Herbert Xu wrote:
> > The arc4 algorithm requires storing state in the request context
> > in order to allow more than one encrypt/decrypt operation. As this
> > driver does not seem to do that, it means that using it for m
As it stands the chacha state array is made 12 bytes bigger on
x86 in order for it to be 16-byte aligned. However, the array
is not actually aligned until it hits the x86 code.
This patch moves the alignment to where the state array is defined.
To do so a macro DEFINE_CHACHA_STATE has been added
34 matches
Mail list logo
