On Wed, May 20, 2020 at 12:45:56PM -0400, st...@rowland.harvard.edu wrote:
> On Wed, May 20, 2020 at 03:42:17PM +, Sverdlin, Alexander (Nokia -
> DE/Ulm) wrote:
> > Hello Dinghao,
> >
> > On Wed, 2020-05-20 at 21:29 +0800, Dinghao Liu wrote:
> > > pm_runtime_get_sync() increments the runtime
On 2020/5/27 下午5:01, Greg Kroah-Hartman wrote:
On Tue, May 26, 2020 at 07:49:09PM +0800, Zhangfei Gao wrote:
Calling pci_fixup_iommu in iommu_fwspec_init, which alloc
iommu_fwnode. Some platform devices appear as PCI but are
actually on the AMBA bus, and they need fixup in
drivers/pci/quirks.
Hi, Bjorn
On 2020/5/28 上午2:18, Bjorn Helgaas wrote:
On Tue, May 26, 2020 at 07:49:07PM +0800, Zhangfei Gao wrote:
Some platform devices appear as PCI but are actually on the AMBA bus,
and they need fixup in drivers/pci/quirks.c handling iommu_fwnode.
Here introducing PCI_FIXUP_IOMMU, which is c
On Tue, May 19, 2020 at 10:45:03PM +0200, Christophe JAILLET wrote:
> When a list is completely iterated with 'list_for_each_entry(x, ...)', x is
> not NULL at the end.
>
> Introduce an intermediate variable and test it instead, in order to
> reliably know if something was found or not.
>
> Fixes
Return -EINVAL if the input digest size and/or cipher
length is zero or the cipher length is not multiple of a block.
These additional parameter checks prevent an undefined device behaviour.
Signed-off-by: Giovanni Cabiddu
---
drivers/crypto/qat/qat_common/qat_algs.c | 15 ++-
1 file
On Wed, May 27, 2020 at 10:37 AM Daniel Jordan
wrote:
>
> Deferred struct page init is a significant bottleneck in kernel boot.
> Optimizing it maximizes availability for large-memory systems and allows
> spinning up short-lived VMs as needed without having to leave them
> running. It also benefi
On Wed, May 27, 2020 at 10:37 AM Daniel Jordan
wrote:
>
> Deferred page init used to report the number of pages initialized:
>
> node 0 initialised, 32439114 pages in 97ms
>
> Tracking this makes the code more complicated when using multiple
> threads. Given that the statistic probably has limi
On Wed, May 27, 2020 at 08:24:35PM +0200, Arnd Bergmann wrote:
> On Wed, May 27, 2020 at 6:42 PM Nathan Chancellor
> wrote:
> >
> > On Wed, May 27, 2020 at 04:17:40PM +0200, Arnd Bergmann wrote:
> > > The clang integrated assembler complains about movzxw:
> > >
> > > arch/x86/crypto/crc32c-pcl-int
Am Mittwoch, 27. Mai 2020, 04:21:31 CEST schrieb Bhat, Jayalakshmi Manjunath:
Hi Jayalakshmi,
> Hi All,
>
> I was going through libkcapi APIs to see if it can be used for DRBG CAVS
> validation. But I am thinking it cannot be. I also found cavs_driver.pl,
> this seems to depend on some kernel mo
On Wed, May 27, 2020 at 6:42 PM Nathan Chancellor
wrote:
>
> On Wed, May 27, 2020 at 04:17:40PM +0200, Arnd Bergmann wrote:
> > The clang integrated assembler complains about movzxw:
> >
> > arch/x86/crypto/crc32c-pcl-intel-asm_64.S:173:2: error: invalid instruction
> > mnemonic 'movzxw'
> >
> >
On Tue, May 26, 2020 at 07:49:07PM +0800, Zhangfei Gao wrote:
> Some platform devices appear as PCI but are actually on the AMBA bus,
> and they need fixup in drivers/pci/quirks.c handling iommu_fwnode.
> Here introducing PCI_FIXUP_IOMMU, which is called after iommu_fwnode
> is allocated, instead o
Using padata during deferred init has only been tested on x86, so for
now limit it to this architecture.
If another arch wants this, it can find the max thread limit that's best
for it and override deferred_page_init_max_threads().
Signed-off-by: Daniel Jordan
Tested-by: Josh Triplett
---
arch
padata_driver_exit() is unnecessary because padata isn't built as a
module and doesn't exit.
padata's init routine will soon allocate memory, so getting rid of the
exit function now avoids pointless code to free it.
Signed-off-by: Daniel Jordan
Tested-by: Josh Triplett
---
kernel/padata.c | 6
Thanks to Alex for his continued review and Josh for running v2! Please
continue to review and test, and acks for the padata parts would be
appreciated.
Daniel
--
Deferred struct page init is a bottleneck in kernel boot--the biggest
for us and probably others. Optimizing it maximizes availabil
padata allocates per-CPU, per-instance work structs for parallel jobs.
A do_parallel call assigns a job to a sequence number and hashes the
number to a CPU, where the job will eventually run using the
corresponding work.
This approach fit with how padata used to bind a job to each CPU
round-robin,
Add Documentation for multithreaded jobs.
Signed-off-by: Daniel Jordan
Tested-by: Josh Triplett
---
Documentation/core-api/padata.rst | 41 +++
1 file changed, 31 insertions(+), 10 deletions(-)
diff --git a/Documentation/core-api/padata.rst
b/Documentation/core-api
Deferred page init used to report the number of pages initialized:
node 0 initialised, 32439114 pages in 97ms
Tracking this makes the code more complicated when using multiple
threads. Given that the statistic probably has limited value,
especially since a zone grows on demand so that the page
padata will soon initialize the system's struct pages in parallel, so it
needs to be ready by page_alloc_init_late().
The error return from padata_driver_init() triggers an initcall warning,
so add a warning to padata_init() to avoid silent failure.
Signed-off-by: Daniel Jordan
Tested-by: Josh T
Deferred struct page init is a significant bottleneck in kernel boot.
Optimizing it maximizes availability for large-memory systems and allows
spinning up short-lived VMs as needed without having to leave them
running. It also benefits bare metal machines hosting VMs that are
sensitive to downtime
Sometimes the kernel doesn't take full advantage of system memory
bandwidth, leading to a single CPU spending excessive time in
initialization paths where the data scales with memory size.
Multithreading naturally addresses this problem.
Extend padata, a framework that handles many parallel yet s
On Wed, May 27, 2020 at 04:17:40PM +0200, Arnd Bergmann wrote:
> The clang integrated assembler complains about movzxw:
>
> arch/x86/crypto/crc32c-pcl-intel-asm_64.S:173:2: error: invalid instruction
> mnemonic 'movzxw'
>
> It seems that movzwq is the mnemonic that it expects instead,
> and this
The clang integrated assembler complains about movzxw:
arch/x86/crypto/crc32c-pcl-intel-asm_64.S:173:2: error: invalid instruction
mnemonic 'movzxw'
It seems that movzwq is the mnemonic that it expects instead,
and this is what objdump prints when disassembling the file.
Fixes: 6a8ce1ef3940 ("c
Attn:
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Als
On 2020/5/27 下午5:53, Arnd Bergmann wrote:
On Wed, May 27, 2020 at 11:00 AM Greg Kroah-Hartman
wrote:
On Tue, May 26, 2020 at 07:49:07PM +0800, Zhangfei Gao wrote:
Some platform devices appear as PCI but are actually on the AMBA bus,
Why would these devices not just show up on the AMBA bus
Hi Colin,
On 5/27/2020 4:59 PM, Colin King wrote:
From: Colin Ian King
Variable iv is being assigned twice with the same value, the first
assignment is redundant and can be removed and instead keep the
latter assignment of iv as it is closer to the point it is being
used.
Addresses-Coverity:
Attn:
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von unseren ernannten Zonal Managern verspätet kontaktiert haben. Bitte
beachten Sie, dass Sie qualifiziert sind, die Zahlung von 900.000,00 USD an der
ATM-Karte mit neunhunderttausend Dollar zu erhalten.
Als
As the hardware acceleration for the omap-sham algos is not available
from userspace, force kernel driver usage. Without this flag in place,
openssl 1.1 implementation thinks it can accelerate sha algorithms on
omap devices directly from userspace.
Signed-off-by: Tero Kristo
---
drivers/crypto/o
Running the self test suite for omap-aes with extra tests enabled causes
huge spam with the tag message wrong indicators. With self tests, this
is fine as there are some tests that purposedly pass bad data to the
driver. Also, returning -EBADMSG from the driver is enough, so remove the
dev_err mess
With very small data sizes, the whole data can end up in the xmit
buffer. This code path does not set the sg_len properly which causes the
core dma framework to crash. Fix by adding the proper size in place.
Also, the data length must be a multiple of block-size, so extend the
DMA data size while h
In case buffers are copied from userspace, directly accessing the page
will most likely fail because it hasn't been mapped into the kernel
memory space. Fix the issue by forcing a kmap / kunmap within the
cleanup functionality.
Signed-off-by: Tero Kristo
---
v3:
- Added PageSlab() check to the
The ctx internal buffer can only hold buflen amount of data, don't try
to copy over more than that. Also, initialize the context sg pointer
if we only have data in the context internal buffer, this can happen
when closing a hash with certain data amounts.
Signed-off-by: Tero Kristo
---
drivers/c
Hi,
Resent the whole series as-per request. Only patch changed compared to
v2 [1] is patch #3. Cache flushing logic has been fixed on it based on
comments.
-Tero
[1] https://patchwork.kernel.org/cover/11540265/
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Busin
The current implementation of the multiple accelerator core support for
OMAP SHA does not work properly. It always picks up the first probed
accelerator core if this is available, and rest of the book keeping also
gets confused if there are two cores available. Add proper load
balancing support for
Most of the OMAP family SoCs contain two instances for AES core, which
causes the remove callbacks to be also done twice when driver is
removed. Fix the algorithm unregister callbacks to take into account the
number of algorithms still registered to avoid removing these twice.
Signed-off-by: Tero
Eric Curtin wrote:
> Hope I'm not bothering you. I'm looking for a masters thesis idea, ...
Here's a report claiming 70% of security bugs involve memory errors.
https://www.zdnet.com/article/chrome-70-of-all-security-bugs-are-memory-safety-issues/
Build a tool to find or fix those?
Another repo
From: Colin Ian King
Variable iv is being assigned twice with the same value, the first
assignment is redundant and can be removed and instead keep the
latter assignment of iv as it is closer to the point it is being
used.
Addresses-Coverity: ("Unused value")
Signed-off-by: Colin Ian King
---
Hi Sandy,
I actually have worked quite a bit with IPsec, it's not a protocol I'm
a huge fan of, it's use of multiple ports make it difficult to work
with middleboxs (be it load-balancers, TLS interceptors, reverse
proxies, proxies, firewalls, routers, switches, etc.). I've even seen
issues where s
On Wed, May 27, 2020 at 11:00 AM Greg Kroah-Hartman
wrote:
>
> On Tue, May 26, 2020 at 07:49:07PM +0800, Zhangfei Gao wrote:
> > Some platform devices appear as PCI but are actually on the AMBA bus,
>
> Why would these devices not just show up on the AMBA bus and use all of
> that logic instead of
On Tue, May 26, 2020 at 11:09:57PM +0800, Zhangfei Gao wrote:
> Hi, Christoph
>
> On 2020/5/26 下午10:46, Christoph Hellwig wrote:
> > On Tue, May 26, 2020 at 07:49:08PM +0800, Zhangfei Gao wrote:
> > > Some platform devices appear as PCI but are actually on the AMBA bus,
> > > and they need fixup i
On Tue, May 26, 2020 at 07:49:09PM +0800, Zhangfei Gao wrote:
> Calling pci_fixup_iommu in iommu_fwspec_init, which alloc
> iommu_fwnode. Some platform devices appear as PCI but are
> actually on the AMBA bus, and they need fixup in
> drivers/pci/quirks.c handling iommu_fwnode.
> So calling pci_fix
On Tue, May 26, 2020 at 07:49:07PM +0800, Zhangfei Gao wrote:
> Some platform devices appear as PCI but are actually on the AMBA bus,
Why would these devices not just show up on the AMBA bus and use all of
that logic instead of being a PCI device and having to go through odd
fixes like this?
than
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