loop-AES changes since previous release:
- Worked around kernel interface changes on 5.3 kernels
- Worked around kernel interface changes on RHEL8 / CentOS8 4.18 kernels
bzip2 compressed tarball is here:
http://loop-aes.sourceforge.net/loop-AES/loop-AES-v3.7p.tar.bz2
md5sum a8e8f2c3fe27b6
On Sat, 14 Sep 2019 14:02:55 -0700, Tony Lindgren wrote:
> Commit 0ed266d7ae5e ("clk: ti: omap3: cleanup unnecessary clock aliases")
> removed old omap3 clock framework aliases but caused omap3-rom-rng to
> stop working with clock not found error.
>
> Based on discussions on the mailing list it wa
On Mon, Sep 30, 2019 at 4:14 AM Marc Gonzalez wrote:
>
> Two statements above have raised at least one of my eyebrows.
>
> 1) France has laws that require backdoors.
No. But France has a long history on being bad on encryption policies.
They've gotten better, thankfully.
France was one of the co
> -Original Message-
> From: Arnd Bergmann
> Sent: Monday, September 30, 2019 10:12 PM
> To: Pascal Van Leeuwen
> Cc: Antoine Tenart ; Herbert Xu
> ;
> David S. Miller ; Pascal van Leeuwen
> ; Ard
> Biesheuvel ; Eric Biggers ;
> linux-
> cry...@vger.kernel.org; linux-ker...@vger.kernel
On Mon, Sep 30, 2019 at 9:04 PM Pascal Van Leeuwen
wrote:
> > Alternatively, it should be possible to shrink these allocations
> > as the extra buffers appear to be largely unnecessary, but doing
> > this would be a much more invasive change.
> >
> Actually, for HMAC-SHA512 you DO need all that b
On Mon, 30 Sep 2019 at 18:32, Guenter Roeck wrote:
>
> On Wed, Aug 21, 2019 at 05:32:51PM +0300, Ard Biesheuvel wrote:
> > Instead of relying on the CTS template to wrap the accelerated CBC
> > skcipher, implement the ciphertext stealing part directly.
> >
> > Signed-off-by: Ard Biesheuvel
>
> Fo
> -Original Message-
> From: Arnd Bergmann
> Sent: Monday, September 30, 2019 2:15 PM
> To: Antoine Tenart ; Herbert Xu
> ;
> David S. Miller
> Cc: Arnd Bergmann ; Pascal Van Leeuwen
> ; Pascal van
> Leeuwen ; linux-crypto@vger.kernel.org;
> linux-ker...@vger.kernel.org
> Subject: [PAT
> -Original Message
> From: Linus Torvalds
> Sent: Friday, September 27, 2019 6:24 PM
> To: Pascal Van Leeuwen
> Cc: Ard Biesheuvel ; Linux Crypto Mailing List
> cry...@vger.kernel.org>; Linux ARM ;
> Herbert Xu
> ; David Miller ; Greg KH
> ; Jason A . Donenfeld ; Samuel
> Neves
> ; D
> -Original Message-
> From: Arnd Bergmann
> Sent: Monday, September 30, 2019 2:15 PM
> To: Antoine Tenart ; Herbert Xu
> ;
> David S. Miller
> Cc: Arnd Bergmann ; Pascal Van Leeuwen
> ; Pascal
> van Leeuwen ; Ard Biesheuvel
> ; Eric Biggers
> ; linux-crypto@vger.kernel.org;
> linux-k
On Wed, Aug 21, 2019 at 05:32:51PM +0300, Ard Biesheuvel wrote:
> Instead of relying on the CTS template to wrap the accelerated CBC
> skcipher, implement the ciphertext stealing part directly.
>
> Signed-off-by: Ard Biesheuvel
For arm:allmodconfig built with gcc 9.2.0, this patch results in
ar
On Mon, 30 Sep 2019 15:17:02 +0100
Jonathan Cameron wrote:
> On Mon, 30 Sep 2019 16:49:21 +0800
> Tian Tao wrote:
>
> > This patch fixes the following warnings:
> > drivers/crypto/ccree/cc_aead.c:630:5-12: WARNING: Unsigned expression
> > compared with zero: seq_len > 0
> >
> > Signed-off-by:
On Mon, 30 Sep 2019 16:49:21 +0800
Tian Tao wrote:
> This patch fixes the following warnings:
> drivers/crypto/ccree/cc_aead.c:630:5-12: WARNING: Unsigned expression
> compared with zero: seq_len > 0
>
> Signed-off-by: Tian Tao
Apologies, I should have looked into this in more depth when you a
Hi,
there's another implementation of blake2s in the list from today, I was waiting
with my patches post rc1 so I'm sending it as it was. My usecase is for
'BLAKE2b'.
---
The patch brings support of several BLAKE2 algorithms (2b, 2s, various digest
lengths). The in-tree user will be btrfs (for
The patch brings support of several BLAKE2 algorithms (2b, 2s, various
digest lengths). The in-tree user will be btrfs (for checksumming),
we're going to use the BLAKE2b-256 variant. It would be ideal if the
patches get merged to 5.5, thats our target to release the support of
new hashes.
The code
On Mon, Sep 30, 2019 at 02:14:35PM +0200, Arnd Bergmann wrote:
> When both PCI and OF are disabled, no drivers are registered, and
> we get some unused-function warnings:
>
> drivers/crypto/inside-secure/safexcel.c:1221:13: error: unused function
> 'safexcel_unregister_algorithms' [-Werror,-Wunus
When both PCI and OF are disabled, no drivers are registered, and
we get some unused-function warnings:
drivers/crypto/inside-secure/safexcel.c:1221:13: error: unused function
'safexcel_unregister_algorithms' [-Werror,-Wunused-function]
static void safexcel_unregister_algorithms(struct safexcel_c
safexcel_aead_setkey() contains three large stack variables, totalling
slightly more than the 1024 byte warning limit:
drivers/crypto/inside-secure/safexcel_cipher.c:303:12: error: stack frame size
of 1032 bytes in function 'safexcel_aead_setkey' [-Werror,-Wframe-larger-than=]
The function alrea
A previous fixup avoided an unused variable warning but replaced
it with a slightly scarier warning:
drivers/crypto/inside-secure/safexcel.c:1100:6: error: variable 'irq' is used
uninitialized whenever 'if' condition is false
[-Werror,-Wsometimes-uninitialized]
This is harmless as it is impossi
On Sun, 29 Sep 2019 at 19:38, Ard Biesheuvel wrote:
...
>
> Patches can be found here:
> https://git.kernel.org/pub/scm/linux/kernel/git/ardb/linux.git/log/?h=wireguard-crypto-library-api
>
Note: I touched up some minor issues spotted by the build robots, so
if anyone pulled this for testing, you
On Mon, 30 Sep 2019 at 13:01, Masahiro Yamada
wrote:
>
> On Mon, Sep 30, 2019 at 2:41 AM Ard Biesheuvel
> wrote:
> >
> > In order to use 128-bit integer arithmetic in C code, the architecture
> > needs to have declared support for it by setting ARCH_SUPPORTS_INT128,
> > and it requires a version
[ Trimming recipients list ]
On 27/09/2019 18:23, Linus Torvalds wrote:
> It's not the crypto engine that is part of the untrusted hardware.
> It's the box itself, and the manufacturer, and you having to trust
> that the manufacturer didn't set up some magic knocking sequence to
> disable the enc
On Mon, Sep 30, 2019 at 2:41 AM Ard Biesheuvel
wrote:
>
> In order to use 128-bit integer arithmetic in C code, the architecture
> needs to have declared support for it by setting ARCH_SUPPORTS_INT128,
> and it requires a version of the toolchain that supports this at build
> time. This is why all
HiSilicon HPRE engine supports PCI SRIOV. This patch enable
this feature. User can enable VFs and pass through them to VM,
same HPRE driver can work in VM to provide RSA and DH algorithms
by crypto akcipher and kpp interfaces.
Signed-off-by: Zaibo Xu
Signed-off-by: Hui tang
---
drivers/crypto/h
Here adds maintainer information for high performance RSA
engine (HPRE) driver.
Signed-off-by: Zaibo Xu
---
MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 8671e1e..37a73ff 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -7364,6 +7364,15 @@
HiSilicon HPRE engine driver uses debugfs to provide debug information,
the usage can be found in /Documentation/ABI/testing/debugfs-hisi-hpre.
Signed-off-by: Zaibo Xu
Signed-off-by: Hui Tang
---
drivers/crypto/hisilicon/hpre/hpre.h | 36 ++-
drivers/crypto/hisilicon/hpre/hpre_main.c | 42
The HiSilicon HPRE accelerator implements RSA and DH algorithms. It
uses Hisilicon QM as interface to CPU.
This patch provides PCIe driver to the accelerator and registers its
algorithms to crypto akcipher and kpp interfaces.
Signed-off-by: Zaibo Xu
Signed-off-by: Hui Tang
---
drivers/crypto/h
Add debugfs descriptions for HiSilicon HPRE driver.
Signed-off-by: Zaibo Xu
Signed-off-by: Hui Tang
---
Documentation/ABI/testing/debugfs-hisi-hpre | 57 +
1 file changed, 57 insertions(+)
create mode 100644 Documentation/ABI/testing/debugfs-hisi-hpre
diff --git a/
This series adds HiSilicon high performance RSA engine(HPRE) driver
in crypto subsystem. HPRE driver provides PCIe hardware device initiation
with RSA and DH algorithms registered to Crypto. Meanwhile, some debug
supporting of DebugFS is given.
Zaibo Xu (5):
crypto: hisilicon - add HiSilicon HPR
This patch fixes the following warnings:
drivers/crypto/ccree/cc_aead.c:630:5-12: WARNING: Unsigned expression
compared with zero: seq_len > 0
Signed-off-by: Tian Tao
---
drivers/crypto/ccree/cc_aead.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/crypto/ccree/cc_ae
On 2019-09-30 04:42:06 [+0200], Jason A. Donenfeld wrote:
> Hi Sebastian, Thomas,
Hi Jason,
> On Sun, Sep 29, 2019 at 7:39 PM Ard Biesheuvel
> wrote:
> > + for (;;) {
> > + const size_t blocks = min_t(size_t, nblocks,
> > + PAGE_SIZE /
From: Shukun Tan
Add a module parameter for zip driver to set the number of SGE in one SGL.
Signed-off-by: Shukun Tan
Signed-off-by: Zhou Wang
---
drivers/crypto/hisilicon/qm.h | 2 ++
drivers/crypto/hisilicon/sgl.c| 2 +-
drivers/crypto/hisilicon/zip/zip_crypto.c |
As HW SGL can be seen as a data format of QM's sqe, we merge sgl code into
qm module and rename it as hisi_qm, which reduces the number of module and
make the name less generic.
This patch also modify the interface of SGL:
- Create/free hisi_acc_sgl_pool inside.
- Let user to pass the SGE number
This patch fixes some misc problems in sgl codes, e.g. missing static,
sparse error and input parameter check.
Signed-off-by: Zhou Wang
Signed-off-by: Shukun Tan
---
drivers/crypto/hisilicon/sgl.c | 40 ++--
1 file changed, 22 insertions(+), 18 deletions(-)
When disabling SMMU, it may fail to allocate large continuous memory. This
patch fixes this by allocating memory as blocks.
Signed-off-by: Zhou Wang
Signed-off-by: Shukun Tan
---
drivers/crypto/hisilicon/sgl.c | 83 ++
1 file changed, 68 insertions(+), 15
This series fixes some preblems in sgl code. The main change is merging sgl
code into hisi_qm module.
These problem are also fixed:
- Let user driver to pass the configure of sge number in one sgl when
creating hardware sgl resources.
- When disabling SMMU, it may fail to allocate large cont
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