In ccp_run_sha_cmd, if the type of sha is invalid, the allocated
hmac_buf should be released.
Signed-off-by: Navid Emamdoost
---
drivers/crypto/ccp/ccp-ops.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/crypto/ccp/ccp-ops.c b/drivers/crypto/ccp/ccp-ops.c
index 9bc3c62157d7..cff16f
In general we should check for GP device instead of HS device unless
the other options such as EMU are also checked. Otherwise omap3-rom-rng
won't probe on few of the old n900 macro boards still in service in
automated build and boot test systems.
Cc: Aaro Koskinen
Cc: Adam Ford
Cc: Pali Rohár
Hi all,
Here are fixes and improvments for omap3-rom-rng that's been broken for
a while.
The first four patches get it working, and then the last two patches add
support for runtime PM.
Regards,
Tony
Tony Lindgren (6):
ARM: OMAP2+: Check omap3-rom-rng for GP device instead of HS device
hw
When unloading omap3-rom-rng, we'll get the following:
WARNING: CPU: 0 PID: 100 at drivers/clk/clk.c:948 clk_core_disable
This is because the clock is already disabled by omap3_rom_rng_idle().
Also, we should not call prepare and unprepare except during init, and
only call enable and disable dur
Nowadays we have runtime PM, and we can use it with autosuspend_timeout
to idle things automatically. This allows us to get rid of the custom
PM implementation.
We enable clocks and init RNG in runtime_resume, and reset RNG and
disable clocks in runtime_suspend. And then omap3_rom_rng_read()
becom
Similar to commit 62f95ae805fa ("hwrng: omap - Set default quality")
we need to initialize the default quality for the RNG to be used.
The symptoms of this problem is that doing hd /dev/random does not
produce much data at all.
Signed-off-by: Tony Lindgren
---
drivers/char/hw_random/omap3-rom-r
Commit 0ed266d7ae5e ("clk: ti: omap3: cleanup unnecessary clock aliases")
removed old omap3 clock framework aliases but caused omap3-rom-rng to
stop working with clock not found error.
Based on discussions on the mailing list it was requested by Tero Kristo
that it would be best to fix this issue
Let's update omap3-rom-rng to use standard driver data to make it easier
to add runtime PM support in the following patch. Just use it for the
clock for now, but still keep also old rng_clk still around. We will
remove delayed work and rng_clk with runtime PM in the next patch.
Signed-off-by: Tony
This patch adds support for the authenc(hmac(sha1),cbc(des)) aead
changes since v1:
- rebased on top of DES changes made to cryptodev/master
Signed-off-by: Pascal van Leeuwen
---
drivers/crypto/inside-secure/safexcel.c| 1 +
drivers/crypto/inside-secure/safexcel.h| 1 +
driver
This patch adds support for the authenc(hmac(sha224),cbc(des)),
authenc(hmac(sha256),cbc(des)), authenc(hmac(sha384),cbc(des))
and authenc(hmac(sha512),cbc(des)) aead's
changes since v1:
- nothing
Signed-off-by: Pascal van Leeuwen
---
drivers/crypto/inside-secure/safexcel.c| 4 +
driv
This patch adds support for the authenc(hmac(sha224),cbc(des3_ede)),
authenc(hmac(sha256),cbc(des3_ede)), authenc(hmac(sha384),cbc(des3_ede))
and authenc(hmac(sha512),cbc(des3_ede)) aead's
changes since v1:
- nothing
Signed-off-by: Pascal van Leeuwen
---
drivers/crypto/inside-secure/safexcel.c
This patchset adds the remaining authencs with DES or 3DES currently
supported with vectors by testmgr.
The patchset has been tested with the eip197c_iewxkbc configuration on the
Xilinx VCU118 development boardi as well as on the Macchiatobin board,
including the testmgr extra tests.
changes sinc
This patch adds support for hmac(sha3-224), hmac(sha3-256), hmac(sha3-384)
and hmac(sha3-512) authentication algorithms.
The patch has been tested with the eip197c_iewxkbc configuration on the
Xilinx VCU118 development board, including the testmgr extra tests.
changes since v1:
- nothing
Signed-
This patchset adds support for all flavours of sha3-xxx and hmac(sha3-xxx)
ahash algorithms.
The patchset has been tested with the eip197c_iewxkbc configuration on the
Xilinx VCU118 development board, including the testmgr extra tests.
changes snce v1:
- fixed crypto/Kconfig so that generic fallb
Due to the addition of SHA3 and HMAC-SHA3 support to the inside-secure
driver, it now depends on CRYPTO_SHA3. Added reference.
changes since v1:
- added missing dependency to crypto/Kconfig
Signed-off-by: Pascal van Leeuwen
---
drivers/crypto/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff
This patch adds support for sha3-224, sha3-256, sha3-384 and sha3-512
basic hashes.
The patch has been tested with the eip197c_iewxkbc configuration on the
Xilinx VCU118 development board, including the testmgr extra tests.
changes since v1:
- nothing
Signed-off-by: Pascal van Leeuwen
---
driv
This patch adds support for the authenc(hmac(sha1),cbc(sm4)),
authenc(hmac(sm3),cbc(sm4)), authenc(hmac(sha1),rfc3686(ctr(sm4))),
and authenc(hmac(sm3),rfc3686(ctr(sm4))) aead ciphersuites.
These are necessary to support IPsec according to the Chinese standard
GM/T 022-1014 - IPsec VPN specificatio
On 04.09.2019 05:35, Andrey Smirnov wrote:
> Returning -EBUSY from platform device's .remove() callback won't stop
> the removal process, so the code in caam_jr_remove() is not going to
> have the desired effect of preventing JR from being removed.
>
> In order to be able to deal with removal of t
Extend driver support with chacha20, rfc7539(chacha20,poly1305) and
rfc7539esp(chacha20,poly1305) ciphers.
The patchset has been tested with the eip197c_iesb and eip197c_iewxkbc
configurations on the Xilinx VCU118 development board, including the
crypto extra tests.
Note that this patchset applies
This patch adds support for the Chacha20-Poly1305 cipher suite.
It adds both the basic rfc7539(chacha20,poly1305) as well as the
rfc7539esp(chacha20,poly1305) variant for IPsec ESP acceleration.
changes since v1:
- rebased on top of DES library changes done on cryptodev/master
- fixed crypto/Kconf
Due to the addition of Chacha20-Poly1305 support to the inside-secure
driver, it now depends on CRYPTO_CHACHA20POLY1305. Added reference.
changes since v1:
- added missing dependency to crypto/Kconfig
changes since v2:
- nothing
Signed-off-by: Pascal van Leeuwen
---
drivers/crypto/Kconfig | 3
Added support for the CHACHA20 skcipher algorithm.
Tested on an eip197c-iesb configuration in the Xilinx VCU118 devboard,
passes all testmgr vectors plus the extra fuzzing tests.
changes since v1:
- rebased on top of DES library changes done on cryptodev/master
- fixed crypto/Kconfig so that gene
Due to the addition of Chacha20-Poly1305 support to the inside-secure
driver, it now depends on CRYPTO_CHACHA20POLY1305. Added reference.
changes since v1:
- added missing dependency to crypto/Kconfig
Signed-off-by: Pascal van Leeuwen
---
drivers/crypto/Kconfig | 3 ++-
1 file changed, 2 insert
This patch adds support for the Chacha20-Poly1305 cipher suite.
It adds both the basic rfc7539(chacha20,poly1305) as well as the
rfc7539esp(chacha20,poly1305) variant for IPsec ESP acceleration.
changes since v1:
- rebased on top of DES changes done to cryptodev/master
Signed-off-by: Pascal van L
Added support for the CHACHA20 skcipher algorithm.
Tested on an eip197c-iesb configuration in the Xilinx VCU118 devboard,
passes all testmgr vectors plus the extra fuzzing tests.
changes since v1:
- rebased on top of DES changes done to cryptodev/master
Signed-off-by: Pascal van Leeuwen
---
dri
Extend driver support with chacha20, rfc7539(chacha20,poly1305) and
rfc7539esp(chacha20,poly1305) ciphers.
The patchset has been tested with the eip197c_iesb and eip197c_iewxkbc
configurations on the Xilinx VCU118 development board, including the
crypto extra tests.
Note that this patchset applies
The next version of Clang will start policing compiler command line
options, and will reject combinations of -march and -mfpu that it
thinks are incompatible.
This results in errors like
clang-10: warning: ignoring extension 'crypto' because the 'armv7-a'
architecture does not support it [-Wi
> -Original Message-
> From: Ard Biesheuvel
> Sent: Friday, September 13, 2019 6:24 PM
> To: Pascal Van Leeuwen
> Cc: Pascal van Leeuwen ; open list:HARDWARE RANDOM
> NUMBER
> GENERATOR CORE ; Antoine Tenart
> ; Herbert Xu ; David
> S. Miller
>
> Subject: Re: [PATCH 1/3] crypto: inside
On Fri, 13 Sep 2019 at 17:17, Pascal Van Leeuwen
wrote:
>
> > -Original Message-
> > From: Ard Biesheuvel
> > Sent: Friday, September 13, 2019 5:27 PM
> > To: Pascal van Leeuwen
> > Cc: open list:HARDWARE RANDOM NUMBER GENERATOR CORE
> > ;
> > Antoine Tenart ; Herbert Xu
> > ;
> > Davi
Extend driver support with sm3 and hmac(sm3) ahash support.
Also add GM/T 0042-2015 hmac(sm3) testvectors to the testmgr.
The patchset has been tested with the eip197c_iewxkbc configuration
on the Xilinx VCU118 development board, including the crypto extra tests.
Note that this patchset applies on
Added support for the hmac(sm3) ahash authentication algorithm
changes since v1:
- added Acked-by tag below, no changes to the source
changes since v2:
- nothing
Acked-by: Antoine Tenart
Signed-off-by: Pascal van Leeuwen
---
drivers/crypto/inside-secure/safexcel.c | 1 +
drivers/crypto/
Added testvectors for the hmac(sm3) ahash authentication algorithm
changes since v1 & v2:
-nothing
Signed-off-by: Pascal van Leeuwen
---
crypto/testmgr.c | 6 ++
crypto/testmgr.h | 56
2 files changed, 62 insertions(+)
diff --git a/
Added support for the SM3 ahash algorithm
changes since v1:
- moved definition of CONTEXT_CONTROL_CRYPTO_ALG_SM3 (0x7) up above 0xf
changes since v2:
- allow compilation if CONFIG_CRYPTO_SM3 is not set
Acked-by: Antoine Tenart
Signed-off-by: Pascal van Leeuwen
---
drivers/crypto/inside-secure
> -Original Message-
> From: Ard Biesheuvel
> Sent: Friday, September 13, 2019 5:27 PM
> To: Pascal van Leeuwen
> Cc: open list:HARDWARE RANDOM NUMBER GENERATOR CORE
> ;
> Antoine Tenart ; Herbert Xu
> ;
> David S. Miller ; Pascal Van Leeuwen
>
> Subject: Re: [PATCH 1/3] crypto: insid
On Fri, 13 Sep 2019 at 16:06, Pascal van Leeuwen wrote:
>
> This patch adds support for the authenc(hmac(sha1),cbc(des)) aead
>
> Signed-off-by: Pascal van Leeuwen
Please make sure your code is based on cryptodev/master before sending
it to the list.
--
Ard.
> ---
> drivers/crypto/inside-sec
This patchset adds the remaining authencs with DES or 3DES currently
supported with vectors by testmgr.
The patchset has been tested with the eip197c_iewxkbc configuration on the
Xilinx VCU118 development boardi as well as on the Macchiatobin board,
including the testmgr extra tests.
Pascal van L
This patch adds support for the authenc(hmac(sha224),cbc(des)),
authenc(hmac(sha256),cbc(des)), authenc(hmac(sha384),cbc(des))
and authenc(hmac(sha512),cbc(des)) aead's
Signed-off-by: Pascal van Leeuwen
---
drivers/crypto/inside-secure/safexcel.c| 4 +
drivers/crypto/inside-secure/safe
This patch adds support for the authenc(hmac(sha1),cbc(des)) aead
Signed-off-by: Pascal van Leeuwen
---
drivers/crypto/inside-secure/safexcel.c| 1 +
drivers/crypto/inside-secure/safexcel.h| 1 +
drivers/crypto/inside-secure/safexcel_cipher.c | 45 ++
3
This patch adds support for the authenc(hmac(sha224),cbc(des3_ede)),
authenc(hmac(sha256),cbc(des3_ede)), authenc(hmac(sha384),cbc(des3_ede))
and authenc(hmac(sha512),cbc(des3_ede)) aead's
Signed-off-by: Pascal van Leeuwen
---
drivers/crypto/inside-secure/safexcel.c| 4 +
drivers/crypt
On Wed, Sep 11, 2019 at 04:51:50PM +0530, Sumit Garg wrote:
> Switch to utilize common heap based tpm_buf code for TPM based
> asymmetric keys rather than using stack based tpm_buf code.
>
> Reported-by: kbuild test robot
> Signed-off-by: Sumit Garg
Can you roll instead a new version of the who
On Thu, Sep 12, 2019 at 09:37:17PM +0100, Chen-Yu Tsai wrote:
> On Thu, Sep 12, 2019 at 9:33 PM Maxime Ripard wrote:
> > On Thu, Sep 12, 2019 at 09:26:27PM +0100, Chen-Yu Tsai wrote:
> > > > >
> > > > > clock-names:
> > > > > items:
> > > > > - const: ahb
> > > > > - const: mod
>
On Fri, Sep 13, 2019 at 10:15:55AM +0200, Corentin Labbe wrote:
> On Sat, Sep 07, 2019 at 07:03:53AM +0300, Maxime Ripard wrote:
> > On Fri, Sep 06, 2019 at 08:45:51PM +0200, Corentin Labbe wrote:
> > > This patch adds the new allwinner crypto configs to sunxi_defconfig
> > >
> > > Signed-off-by: C
This patch adds support for hmac(sha3-224), hmac(sha3-256), hmac(sha3-384)
and hmac(sha3-512) authentication algorithms.
The patch has been tested with the eip197c_iewxkbc configuration on the
Xilinx VCU118 development board, including the testmgr extra tests.
Signed-off-by: Pascal van Leeuwen
-
This patch adds support for sha3-224, sha3-256, sha3-384 and sha3-512
basic hashes.
The patch has been tested with the eip197c_iewxkbc configuration on the
Xilinx VCU118 development board, including the testmgr extra tests.
Signed-off-by: Pascal van Leeuwen
---
drivers/crypto/inside-secure/safe
This patchset adds support for all flavours of sha3-xxx and hmac(sha3-xxx)
ahash algorithms.
The patchset has been tested with the eip197c_iewxkbc configuration on the
Xilinx VCU118 development board, including the testmgr extra tests.
Pascal van Leeuwen (2):
crypto: inside-secure - Add SHA3 fa
On Sun, Sep 08, 2019 at 11:04:26AM +0300, Uri Shir wrote:
> In XTS encryption/decryption the plaintext byte size
> can be >= AES_BLOCK_SIZE. This patch enable the AES-XTS ciphertext
> stealing implementation in ccree driver.
>
> Signed-off-by: Uri Shir
> ---
> drivers/crypto/ccree/cc_cipher.c |
On Fri, Sep 06, 2019 at 04:31:47PM +0200, Pascal van Leeuwen wrote:
> This patchset adds support for non-Marvell hardware, probing the HW
> configuration directly from the HW itself instead of making assumptions
> based on specific Marvell instances and applying appropriate settings.
> This should
On Thu, Sep 05, 2019 at 09:40:20PM -0400, Daniel Jordan wrote:
> v2 -> v3:
> - Rebase onto cryptodev.
>
> v1 -> v2:
> - Updated patch 8 to avoid queueing the reorder work if the next object
>by sequence number isn't ready yet (Herbert)
> - Added Steffen's ack to all but patch 8 since that o
On Fri, Aug 30, 2019 at 02:01:39PM -0700, Andrey Smirnov wrote:
> Add node for CAAM - Cryptographic Acceleration and Assurance Module.
>
> Signed-off-by: Horia Geantă
> Signed-off-by: Andrey Smirnov
> Cc: Cory Tusar
> Cc: Chris Healy
> Cc: Lucas Stach
> Cc: Herbert Xu
> Cc: Shawn Guo
> Cc:
Added testvectors for the rfc3686(ctr(sm4)) skcipher algorithm
changes since v1:
- nothing
Signed-off-by: Pascal van Leeuwen
---
crypto/testmgr.c | 6 ++
crypto/testmgr.h | 29 +
2 files changed, 35 insertions(+)
diff --git a/crypto/testmgr.c b/crypto/testmgr.c
This patch adds support for SM4 in CFB mode, i.e. skcipher cfb(sm4).
changes since v1:
- nothing
Signed-off-by: Pascal van Leeuwen
---
drivers/crypto/inside-secure/safexcel.c| 1 +
drivers/crypto/inside-secure/safexcel.h| 1 +
drivers/crypto/inside-secure/safexcel_cipher.c | 3
Added testvectors for the ofb(sm4) and cfb(sm4) skcipher algorithms
changes since v1:
- nothing
Signed-off-by: Pascal van Leeuwen
---
crypto/testmgr.c | 12 +++
crypto/testmgr.h | 98
2 files changed, 110 insertions(+)
diff --git a/c
This patch adds support for SM4 in ECB mode, i.e. skcipher ecb(sm4).
changes since v1:
- make SAFEXCEL_SM4 case entry explit, using the proper SM4_BLOCK_SIZE
instead of "borrowing" the AES code which "coincidentally" works
Signed-off-by: Pascal van Leeuwen
---
drivers/crypto/inside-secure/saf
This patch adds support for SM4 in CBC mode, i.e. skcipher cbc(sm4).
changes since v1:
- nothing
Signed-off-by: Pascal van Leeuwen
---
drivers/crypto/inside-secure/safexcel.c| 1 +
drivers/crypto/inside-secure/safexcel.h| 1 +
drivers/crypto/inside-secure/safexcel_cipher.c | 3
This patch adds support for SM4 in OFB mode, i.e. skcipher ofb(sm4).
changes since v1:
- nothing
Signed-off-by: Pascal van Leeuwen
---
drivers/crypto/inside-secure/safexcel.c| 1 +
drivers/crypto/inside-secure/safexcel.h| 1 +
drivers/crypto/inside-secure/safexcel_cipher.c | 3
This patch adds support for SM4 in (32 bit) CTR mode, i.e. skcipher
rfc3686(ctr(sm4)).
changes since v1:
- nothing
Signed-off-by: Pascal van Leeuwen
---
drivers/crypto/inside-secure/safexcel.c| 1 +
drivers/crypto/inside-secure/safexcel.h| 1 +
drivers/crypto/inside-secure/saf
Extend driver support with ecb(sm4), cbc(sm4), ofb(sm4), cfb(sm4) and
rfc3686(ctr(sm4)) skcipher algorithms.
Also add ofb(sm4), cfb(sm4) and rfc3686(ctr(sm4)) testvectors to testmgr.
The patchset has been tested with the eip197c_iewxkbc configuration
on the Xilinx VCU118 development board, includin
This patch fixes an unused variable warning from the compiler when the
driver is being compiled without PCI support in the kernel.
changes since v1:
- capture the platform_register_driver error code as well
- actually return the (last) error code
- swapped registration to do PCI first as that's ju
> -Original Message-
> From: linux-crypto-ow...@vger.kernel.org
> On Behalf
> Of Herbert Xu
> Sent: Friday, September 13, 2019 11:21 AM
> To: Pascal van Leeuwen
> Cc: linux-crypto@vger.kernel.org; antoine.ten...@bootlin.com;
> da...@davemloft.net;
> Pascal Van Leeuwen
> Subject: Re: [P
On Thu, Sep 12, 2019 at 12:01:49PM +0300, Tomer Maimon wrote:
> Add Nuvoton NPCM BMC Random Number Generator(RNG) driver.
>
> Signed-off-by: Tomer Maimon
Reviewed-by: Daniel Thompson
Note, you are welcome to preseve this if you have to respin and
change directory based on Vinod's feedback...
On Fri, Sep 06, 2019 at 05:25:14PM +0200, Pascal van Leeuwen wrote:
> This patch fixes an unused variable warning from the compiler when the
> driver is being compiled without PCI support in the kernel.
>
> changes since v1:
> - capture the platform_register_driver error code as well
> - actually
On Fri, Sep 06, 2019 at 05:22:30PM +0200, Arnd Bergmann wrote:
> The only caller of hisi_zip_vf_q_assign() is hidden in an #ifdef,
> so the function causes a warning when CONFIG_PCI_IOV is disabled:
>
> drivers/crypto/hisilicon/zip/zip_main.c:740:12: error: unused function
> 'hisi_zip_vf_q_assign
Hi,
I just noticed that for HMAC-SHA3-224 and HMAC-SHA3-256, the current
testvectors (and the fuzzing) do NOT test ANY case where the key
is larger than the blocksize and thus first needs to be hashed.
The thing is, SHA3-224 has a blocksize of 144 bytes and -256 has a
blocksize of 140 bytes whil
On Sat, Sep 07, 2019 at 07:03:53AM +0300, Maxime Ripard wrote:
> On Fri, Sep 06, 2019 at 08:45:51PM +0200, Corentin Labbe wrote:
> > This patch adds the new allwinner crypto configs to sunxi_defconfig
> >
> > Signed-off-by: Corentin Labbe
> > ---
> > arch/arm/configs/sunxi_defconfig | 2 ++
> > 1
64 matches
Mail list logo
