On Fri, Sep 06, 2019 at 08:45:51PM +0200, Corentin Labbe wrote:
> This patch adds the new allwinner crypto configs to sunxi_defconfig
>
> Signed-off-by: Corentin Labbe
> ---
> arch/arm/configs/sunxi_defconfig | 2 ++
> 1 file changed, 2 insertions(+)
Can you also enable it in arm64's defconfig a
On Fri, Sep 06, 2019 at 08:45:48PM +0200, Corentin Labbe wrote:
> The Crypto Engine is a hardware cryptographic accelerator that supports
> many algorithms.
> It could be found on most Allwinner SoCs.
>
> This patch enables the Crypto Engine on the Allwinner A64 SoC Device-tree.
>
> Signed-off-by:
On Fri, Sep 06, 2019 at 08:45:46PM +0200, Corentin Labbe wrote:
> The Crypto Engine is a hardware cryptographic offloader that supports
> many algorithms.
> It could be found on most Allwinner SoCs.
>
> This patch enables the Crypto Engine on the Allwinner R40 SoC Device-tree.
>
> Signed-off-by: Co
On Fri, Sep 06, 2019 at 08:45:43PM +0200, Corentin Labbe wrote:
> Since a second Allwinner crypto driver will be added, it is better to
> create a dedicated subdirectory.
>
> Signed-off-by: Corentin Labbe
> ---
> MAINTAINERS | 6 ++
> drivers/crypto/Kconfig | 2
On Fri, Sep 06, 2019 at 08:45:45PM +0200, Corentin Labbe wrote:
> This patch adds documentation for Device-Tree bindings for the
> Crypto Engine cryptographic accelerator driver.
>
> Signed-off-by: Corentin Labbe
> ---
> .../bindings/crypto/allwinner,sun8i-ce.yaml | 84 +++
> 1
On Fri, 6 Sep 2019 at 18:56, Herbert Xu wrote:
>
> On Fri, Sep 06, 2019 at 06:32:29PM -0700, Ard Biesheuvel wrote:
> >
> > The point is that doing
> >
> > skcipher_walk_virt(&walk, ...);
> > skcipher_walk_done(&walk, -EFOO);
> >
> > may clobber your data if you are executing in place (unless I am
On Fri, Sep 06, 2019 at 06:32:29PM -0700, Ard Biesheuvel wrote:
>
> The point is that doing
>
> skcipher_walk_virt(&walk, ...);
> skcipher_walk_done(&walk, -EFOO);
>
> may clobber your data if you are executing in place (unless I am
> missing something)
You mean encrypting in place? If you're en
On Fri, 6 Sep 2019 at 18:19, Herbert Xu wrote:
>
> On Fri, Sep 06, 2019 at 05:52:56PM -0700, Ard Biesheuvel wrote:
> >
> > With this change, we still copy out the output in the
> > SKCIPHER_WALK_COPY or SKCIPHER_WALK_SLOW cases. I'd expect the failure
> > case to only do the kunmap()s, but otherwi
On Fri, Sep 06, 2019 at 05:52:56PM -0700, Ard Biesheuvel wrote:
>
> With this change, we still copy out the output in the
> SKCIPHER_WALK_COPY or SKCIPHER_WALK_SLOW cases. I'd expect the failure
> case to only do the kunmap()s, but otherwise not make any changes that
> are visible to the caller.
I
On Thu, 5 Sep 2019 at 20:13, Herbert Xu wrote:
>
> skcipher_walk_done may be called with an error by internal or
> external callers. For those internal callers we shouldn't unmap
> pages but for external callers we must unmap any pages that are
> in use.
>
> This patch distinguishes between the t
On Thu, Aug 29, 2019 at 12:55 PM Thomas Garnier wrote:
>
> On Tue, Aug 6, 2019 at 8:51 AM Peter Zijlstra wrote:
> >
> > On Tue, Aug 06, 2019 at 05:43:47PM +0200, Borislav Petkov wrote:
> > > On Tue, Jul 30, 2019 at 12:12:44PM -0700, Thomas Garnier wrote:
> > > > These patches make some of the cha
> -Original Message-
> From: Arnd Bergmann
> Sent: Friday, September 6, 2019 8:40 PM
> To: Pascal Van Leeuwen
> Cc: Herbert Xu ; David S. Miller
> ; Antoine
> Tenart ; Ard Biesheuvel
> ; Kees Cook
> ; linux-crypto@vger.kernel.org;
> linux-ker...@vger.kernel.org
> Subject: Re: [PATCH 1/
The Crypto Engine is an hardware cryptographic offloader present
on all recent Allwinner SoCs H2+, H3, R40, A64, H5, H6
This driver supports AES cipher in CBC/ECB mode.
Signed-off-by: Corentin Labbe
---
drivers/crypto/allwinner/Kconfig | 26 +
drivers/crypto/allwinner/Makefile
The Crypto Engine is a hardware cryptographic offloader that supports
many algorithms.
It could be found on most Allwinner SoCs.
This patch enables the Crypto Engine on the Allwinner R40 SoC Device-tree.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-r40.dtsi | 11 +++
1 file
The Crypto Engine is a hardware cryptographic accelerator that supports
many algorithms.
This patch enables the Crypto Engine on the Allwinner H6 SoC Device-tree.
Signed-off-by: Corentin Labbe
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++
1 file changed, 10 insertions(+)
di
This patch adds the new allwinner crypto configs to sunxi_defconfig
Signed-off-by: Corentin Labbe
---
arch/arm/configs/sunxi_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index df433abfcb02..d0ab8ba7710a 100644
The Crypto Engine is a hardware cryptographic accelerator that supports
many algorithms.
It could be found on most Allwinner SoCs.
This patch enables the Crypto Engine on the Allwinner A64 SoC Device-tree.
Signed-off-by: Corentin Labbe
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 11
The Crypto Engine is a hardware cryptographic accelerator that supports
many algorithms.
It could be found on most Allwinner SoCs.
This patch enables the Crypto Engine on the Allwinner H5 SoC Device-tree.
Signed-off-by: Corentin Labbe
---
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 11 ++
The Crypto Engine is a hardware cryptographic accelerator that supports
many algorithms.
It could be found on most Allwinner SoCs.
This patch enables the Crypto Engine on the Allwinner H3 SoC Device-tree.
Signed-off-by: Corentin Labbe
---
arch/arm/boot/dts/sun8i-h3.dtsi | 11 +++
1 file
Hello
This patch serie adds support for the Allwinner crypto engine.
The Crypto Engine is the third generation of Allwinner cryptogaphic offloader.
The first generation is the Security System already handled by the
sun4i-ss driver.
The second is named also Security System and is present on A80 and
This patch adds documentation for Device-Tree bindings for the
Crypto Engine cryptographic accelerator driver.
Signed-off-by: Corentin Labbe
---
.../bindings/crypto/allwinner,sun8i-ce.yaml | 84 +++
1 file changed, 84 insertions(+)
create mode 100644
Documentation/devicetree/
Since a second Allwinner crypto driver will be added, it is better to
create a dedicated subdirectory.
Signed-off-by: Corentin Labbe
---
MAINTAINERS | 6 ++
drivers/crypto/Kconfig | 2 ++
drivers/crypto/Makefile | 1 +
drivers/crypto/allwinner/Kconfig
On Fri, Sep 6, 2019 at 6:08 PM Pascal Van Leeuwen
wrote:
> >
> > config CRYPTO_DEV_SAFEXCEL
> > tristate "Inside Secure's SafeXcel cryptographic engine driver"
> > - depends on OF || PCI || COMPILE_TEST
> > + depends on OF || PCI
> >
>
> This seems like it just ignores the problem
This patch fixes an unused variable warning from the compiler when the
driver is being compiled without PCI support in the kernel.
changes since v1:
- capture the platform_register_driver error code as well
- actually return the (last) error code
- swapped registration to do PCI first as that's ju
> -Original Message-
> From: Arnd Bergmann
> Sent: Friday, September 6, 2019 5:22 PM
> To: Herbert Xu ; David S. Miller
> ;
> Antoine Tenart
> Cc: Arnd Bergmann ; Pascal Van Leeuwen
> ; Ard
> Biesheuvel ; Kees Cook ;
> linux-
> cry...@vger.kernel.org; linux-ker...@vger.kernel.org
> Sub
This patch derives the result descriptor fetch count from the actual
FIFO size advertised by the hardware. Fetching result descriptors
one at a time is a performance bottleneck for small blocks, especially
on hardware with multiple pipes. Even moreso if the HW has few rings.
Signed-off-by: Pascal
This patch enables algorithms that did not fit the original 32 bit
FUNCTION_EN register anymore via the FUNCTION2_EN extension reg.
Signed-off-by: Pascal van Leeuwen
---
drivers/crypto/inside-secure/safexcel.c | 2 ++
drivers/crypto/inside-secure/safexcel.h | 1 +
2 files changed, 3 insertions(+
This patch adds automatic EIP97/EIP197 detection, so it does not need to
rely on any static value from the device table anymore. In particular,
the static value from the table won't work for PCI devboards that cannot
be further identified save from this direct hardware probing.
The patch also adds
This patch actually probes the transform record cache data and
administration RAM sizes, instead of making assumptions, and then
configures the TRC based on the actually probed values.
This allows the driver to work with EIP197 HW that has TRC RAM
sizes different from those of the Marvell EIP197B/D
This patch derives the command descriptor fetch count from the actual
FIFO size advertised by the hardware. Fetching command descriptors
one at a time is a performance bottleneck for small blocks, especially
on hardware with multiple pipes. Even moreso if the HW has few rings.
Signed-off-by: Pasca
This patchset adds support for non-Marvell hardware, probing the HW
configuration directly from the HW itself instead of making assumptions
based on specific Marvell instances and applying appropriate settings.
This should get most EIP97/EIP197 instances out there up and running,
albeit not always
This patch corrects the configuration of the EIP197_PE_EIP96_TOKEN_CTRL
register. Previous value was wrong and potentially dangerous.
Signed-off-by: Pascal van Leeuwen
---
drivers/crypto/inside-secure/safexcel.c | 4 ++--
drivers/crypto/inside-secure/safexcel.h | 4 ++--
2 files changed, 4 inser
The only caller of hisi_zip_vf_q_assign() is hidden in an #ifdef,
so the function causes a warning when CONFIG_PCI_IOV is disabled:
drivers/crypto/hisilicon/zip/zip_main.c:740:12: error: unused function
'hisi_zip_vf_q_assign' [-Werror,-Wunused-function]
Move it into the same #ifdef.
Fixes: 79e0
The addition of PCI support introduced multiple randconfig issues.
- When PCI is disabled, some external functions are undeclared:
drivers/crypto/inside-secure/safexcel.c:944:9: error: implicit declaration of
function 'pci_irq_vector' [-Werror,-Wimplicit-function-declaration]
- Also, in the same
> -Original Message-
> From: Herbert Xu
> Sent: Friday, September 6, 2019 3:05 PM
> To: Pascal Van Leeuwen
> Cc: Pascal van Leeuwen ; linux-crypto@vger.kernel.org;
> antoine.ten...@bootlin.com; da...@davemloft.net; Bjorn Helgaas
>
> Subject: Re: [PATCHv2] crypto: inside-secure - Fix unu
On Fri, Sep 06, 2019 at 01:01:19PM +, Pascal Van Leeuwen wrote:
>
> I explicitly DON'T want to abort if the PCI registration fails,
> since that may be irrelevant if the OF registration passes AND
> the device actually happens to be Device Tree.
> So not checking the result value is on purpose
> -Original Message-
> From: linux-crypto-ow...@vger.kernel.org
> On Behalf
> Of Herbert Xu
> Sent: Friday, September 6, 2019 2:19 PM
> To: Pascal van Leeuwen
> Cc: linux-crypto@vger.kernel.org; antoine.ten...@bootlin.com;
> da...@davemloft.net;
> Pascal Van Leeuwen ; Bjorn Helgaas
>
On 9/4/2019 5:35 AM, Andrey Smirnov wrote:
> Irq_of_parse_and_map will return zero in case of error, so add a error
> check for that.
>
> Signed-off-by: Andrey Smirnov
> Cc: Chris Healy
> Cc: Lucas Stach
> Cc: Horia Geantă
> Cc: Herbert Xu
> Cc: Iuliana Prodan
> Cc: linux-crypto@vger.kernel.
On 9/4/2019 5:35 AM, Andrey Smirnov wrote:
> With IRQ requesting being managed by devres we need to make sure that
> we dispose of IRQ mapping after and not before it is free'd (otherwise
> we'll end up with a warning from the kernel). To achieve that simply
> convert IRQ mapping to rely on devres
NULL check before kfree is not needed.
Generated-by: scripts/coccinelle/free/ifnullfree.cocci
Signed-off-by: YueHaibing
---
crypto/essiv.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/crypto/essiv.c b/crypto/essiv.c
index a8befc8..3d3f9d7 100644
--- a/crypto/essiv.c
+++
On Fri, Sep 06, 2019 at 10:07:23AM +0200, Pascal van Leeuwen wrote:
>
> diff --git a/drivers/crypto/inside-secure/safexcel.c
> b/drivers/crypto/inside-secure/safexcel.c
> index e12a2a3..2331b31 100644
> --- a/drivers/crypto/inside-secure/safexcel.c
> +++ b/drivers/crypto/inside-secure/safexcel.c
>
On 9/4/2019 5:35 AM, Andrey Smirnov wrote:
> In order to access IP block's registers we need to enable appropriate
> clocks first, otherwise we are risking hanging the CPU.
>
> The problem becomes very apparent when trying to use CAAM driver built
> as a kernel module. In that case caam_probe() ge
On 8/31/2019 12:01 AM, Andrey Smirnov wrote:
> Add node for CAAM - Cryptographic Acceleration and Assurance Module.
>
> Signed-off-by: Horia Geantă
> Signed-off-by: Andrey Smirnov
> Cc: Cory Tusar
> Cc: Chris Healy
> Cc: Lucas Stach
> Cc: Herbert Xu
> Cc: Shawn Guo
> Cc: Iuliana Prodan
> C
This patch fixes an unused variable warning from the compiler when the
driver is being compiled without PCI support in the kernel.
changes since v1:
- capture the platform_register_driver error code as well
- actually return the (last) error code
- swapped registration to do PCI first as that's ju
On Wed, Sep 04, 2019 at 05:40:22PM +, Kalyani Akula wrote:
> Hi Corentin,
>
> Thanks for the review comments.
> Please find my response/queries inline.
>
> > -Original Message-
> > From: Corentin Labbe
> > Sent: Monday, September 2, 2019 12:29 PM
> > To: Kalyani Akula
> > Cc: herb..
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