From: Eric Biggers
The change to encrypt a fifth ChaCha block using scalar instructions
caused the chacha20-neon, xchacha20-neon, and xchacha12-neon self-tests
to start failing on big endian arm64 kernels. The bug is that the
keystream block produced in 32-bit scalar registers is directly XOR'd
I ran the crypto self-tests on big endian arm and arm64 kernels in QEMU.
The arm64 implementation of ChaCha (and XChaCha) is failing, so this
series fixes it.
Please consider sending to Linus for v5.0 if there's time, as this fixes
commits that are new in v5.0.
Eric Biggers (2):
crypto: arm64/c
From: Eric Biggers
On big endian arm64 kernels, the xchacha20-neon and xchacha12-neon
self-tests fail because hchacha_block_neon() outputs little endian words
but the C code expects native endianness. Fix it to output the words in
native endianness (which also makes it match the arm32 version).
Add AES crypto HW acceleration for Exynos5433, with the help of SlimSSS IP.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Kamil Konieczny
---
drivers/crypto/s5p-sss.c | 50
1 file changed, 46 insertions(+), 4 deletions(-)
diff --git a/drivers/crypto/s
Add DT node for SlimSSS (aka Slim SecuritySubSystem) in Exynos5433 SoC.
The users can use compatibility "samsung,exynos5433-slim-sss".
Signed-off-by: Kamil Konieczny
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/ex
Document DT bindings for crypto Samsung Exynos5433 SlimSSS (Slim Security
SubSystem) IP.
Signed-off-by: Kamil Konieczny
---
.../bindings/crypto/samsung-slimsss.txt | 19 +++
1 file changed, 19 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/samsun
Add slimSSS node to DT and crypto AES support for Exynos5433. Tested on
Exynos5433 board with crypto run-time self tests and with tcrypt with
command insmod tcrypt.ko mode=500 sec=1
Changes since v3:
- moved bindings documentation out from samsung-sss.txt into separate file
samsung-slimsss.txt
On Sat, Feb 16, 2019 at 02:51:24PM +0100, Ard Biesheuvel wrote:
> A couple of fixes for a crash bugs in the scalar SHA code for ARM,
> taken from the OpenSSL project. This is triggered by a binutils
> change, and so they should probably be tagged for all stable (v4.4+)
>
> Ard Biesheuvel (2):
>
On Fri, Feb 15, 2019 at 05:26:33PM +, Lendacky, Thomas wrote:
> The current content of some of the driver messages and the way that they
> are issued results in some confusion, especially in the area of the PSP
> as it relates to SEV support. If SEV is not supported, a message is issued
> that
On Thu, Feb 14, 2019 at 10:27:48AM -0800, Eric Biggers wrote:
> From: Eric Biggers
>
> This is needed to test that the end of the message is zero-padded when
> the length is not a multiple of 16 (NH_MESSAGE_UNIT). It's already
> tested indirectly by the 31-byte Adiantum test vector, but it shoul
zhan...@rock-chips.com wrote:
> From: Zhang Zhijie
>
> In some cases, the nents of src scatterlist is different from
> dst scatterlist. So two variables are used to handle the nents
> of src&dst scatterlist.
>
> Reported-by: Eric Biggers
> Fixes: 433cd2c617bf ("crypto: rockchip - add crypto dri
On Thu, Feb 14, 2019 at 12:03:49AM -0800, Eric Biggers wrote:
> Hello,
>
> This series makes the crypto self-tests test that all CBC and CTR
> implementations update req->iv to contain the IV for the next block.
> This apparently has been a requirement for a long time, but it wasn't
> actually tes
On Thu, Feb 14, 2019 at 10:29:39AM -0800, Eric Biggers wrote:
> From: Eric Biggers
>
> Add 1536 and 4096-byte Adiantum test vectors so that the case where
> there are multiple NH hashes is tested. This is already tested by the
> nhpoly1305 test vectors, but it should be tested at the Adiantum le
On Mon, Feb 11, 2019 at 12:31:31PM -0600, Gustavo A. R. Silva wrote:
> Add missing break statement in order to prevent the code from falling
> through to case S_DIN_to_DES.
>
> This bug was found thanks to the ongoing efforts to enable
> -Wimplicit-fallthrough.
>
> Fixes: 63ee04c8b491 ("crypto: c
On Mon, Feb 11, 2019 at 01:46:11PM +0200, Horia Geantă wrote:
> The main update in this patch set is taking advantage of current DPIO
> (SW portal) implementation, making sure a CPU-affine portal is used.
>
> There is a dependency on Freescale SoC drivers tree:
> https://git.kernel.org/pub/scm/lin
On Mon, Feb 11, 2019 at 12:02:50PM +0100, Sebastian Andrzej Siewior wrote:
> Last user of cdev_list_lock was removed in commit
>
> 6422ccc5fbefb ("crypto/chelsio/chtls: listen fails with multiadapt")
>
> Cc: Atul Gupta
> Cc: Harsh Jain
> Signed-off-by: Sebastian Andrzej Siewior
> ---
> driv
On Mon, Feb 11, 2019 at 04:27:58PM +0200, Gilad Ben-Yossef wrote:
> Commit 1358c13a48c4 ("crypto: ccree - fix resume race condition on init")
> was missing a "inline" qualifier for stub function used when CONFIG_PM
> is not set causing a build warning.
>
> Fixes: 1358c13a48c4 ("crypto: ccree - fix
On 2/20/2019 12:50 PM, Chengguang Xu wrote:
> unlikely has already included in IS_ERR(), so just
> remove redundant likely/unlikely annotation.
>
> Signed-off-by: Chengguang Xu
Reviewed-by: Horia Geantă
Thanks,
Horia
From: Chris Spencer
This is required to support the i.MX8.
Signed-off-by: Chris Spencer
---
drivers/crypto/caam/Makefile | 2 +-
drivers/crypto/caam/ctrl.c | 399 +
drivers/crypto/caam/inst_rng.c | 374 ++
drivers/crypto/caam/
From: Chris Spencer
There are no clocks that the CAAM driver needs to initialise on the
i.MX8.
Signed-off-by: Chris Spencer
---
drivers/crypto/caam/ctrl.c | 180 +++
drivers/crypto/caam/intern.h | 1 +
2 files changed, 99 insertions(+), 82 deletions(-)
diff
From: Chris Spencer
The i.MX8 does not currently have an SoC driver so soc_device_match does
not recognise it. Check the machine compatible instead.
Signed-off-by: Chris Spencer
---
drivers/crypto/caam/ctrl.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/
From: Chris Spencer
The i.MX8 is arm64, but its CAAM DMA address size is 32-bits.
Signed-off-by: Chris Spencer
---
drivers/crypto/caam/ctrl.c| 5 +++-
drivers/crypto/caam/desc_constr.h | 27 +
drivers/crypto/caam/intern.h | 4 +--
drivers/crypto/caam/jr.c
From: Chris Spencer
This patch series adds support for the i.MX8MQ to the CAAM driver. This
is mostly adapted from corresponding changes in the NXP repo. The
patches are based on v5.0-rc7.
RFC for now because I do not have any other boards to test it on.
Hopefully people can verify this change o
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