On Sun, Dec 16, 2018 at 03:00:30PM -0800, Eric Biggers wrote:
> From: Eric Biggers
>
> Fixes: cf718eaa8f9b ("crypto: cavium/nitrox - Enabled Mailbox support")
> Signed-off-by: Eric Biggers
> ---
> drivers/crypto/cavium/nitrox/nitrox_debugfs.h | 3 +--
> 1 file changed, 1 insertion(+), 2 deletio
On Sat, Dec 15, 2018 at 12:42:52PM -0800, Eric Biggers wrote:
> From: Eric Biggers
>
> salsa20-generic doesn't use SIMD instructions or otherwise disable
> preemption, so passing atomic=true to skcipher_walk_virt() is
> unnecessary.
>
> Signed-off-by: Eric Biggers
> ---
> crypto/salsa20_generi
On Sat, Dec 15, 2018 at 12:40:17PM -0800, Eric Biggers wrote:
> From: Eric Biggers
>
> Passing atomic=true to skcipher_walk_virt() only makes the later
> skcipher_walk_done() calls use atomic memory allocations, not
> skcipher_walk_virt() itself. Thus, we have to move it outside of the
> preempt
On Sun, Dec 16, 2018 at 03:55:06PM -0800, Eric Biggers wrote:
> From: Eric Biggers
>
> Remove dead code related to internal IV generators, which are no longer
> used since they've been replaced with the "seqiv" and "echainiv"
> templates. The removed code includes:
>
> - The "givcipher" (GIVCIP
On Thu, Dec 13, 2018 at 08:36:37AM +, Corentin Labbe wrote:
> This patch removes unused dump functions for crypto_user_stats.
> There are remains of the copy/paste of crypto_user_base to
> crypto_user_stat and I forgot to remove them.
>
> Signed-off-by: Corentin Labbe
> ---
> crypto/crypto_u
On Fri, Dec 14, 2018 at 11:19:51AM +, Nagadheeraj Rottela wrote:
> Added support to offload AEAD ciphers to NITROX. Currently supported
> AEAD cipher is 'gcm(aes)'.
>
> Signed-off-by: Nagadheeraj Rottela
> Reviewed-by: Srikanth Jampala
> ---
> drivers/crypto/cavium/nitrox/Makefile
On Thu, Dec 13, 2018 at 07:52:32AM -0200, Fabio Estevam wrote:
> The following build warnings are seen when building for ARM64 allmodconfig:
>
> drivers/crypto/mxc-scc.c:181:20: warning: format '%d' expects argument of
> type 'int', but argument 5 has type 'size_t' {aka 'long unsigned int'}
> [-
On Sat, Dec 15, 2018 at 12:41:53PM -0800, Eric Biggers wrote:
> From: Eric Biggers
>
> skcipher_walk_virt() can still sleep even with atomic=true, since that
> only affects the later calls to skcipher_walk_done(). But,
> skcipher_walk_virt() only has to allocate memory for some input data
> layo
On Mon, Dec 10, 2018 at 04:49:29PM -0700, Nathan Chancellor wrote:
> Clang warns when one enumerated type is implicitly converted to another:
>
> drivers/crypto/ux500/cryp/cryp_core.c:559:5: warning: implicit
> conversion from enumeration type 'enum dma_data_direction' to different
> enumeration t
On Mon, Dec 10, 2018 at 04:49:54PM -0700, Nathan Chancellor wrote:
> Clang warns when one enumerated type is implicitly converted to another:
>
> drivers/crypto/ux500/hash/hash_core.c:169:4: warning: implicit
> conversion from enumeration type 'enum dma_data_direction' to different
> enumeration t
On Tue, Dec 11, 2018 at 04:21:36PM +0530, Harsh Jain wrote:
> It includes Bug Fixes
>
> Harsh Jain (5):
> crypto:chcr: Swap location of AAD and IV sent in WR
> crypto:chcr:Use same value for both channel in single WR
> crypto:chcr: cleanup:send addr as value in function argument
> crypto:c
On Mon, Dec 10, 2018 at 07:56:28PM +, Dave Watson wrote:
> This patch set refactors the x86 aes/gcm AVX crypto routines to
> support true scatter/gather by adding gcm_enc/dec_update methods.
>
> It is similar to the previous SSE patchset starting at e1fd316f.
> Unlike the SSE routines, the A
On Tue, Dec 11, 2018 at 08:11:59AM +, YueHaibing wrote:
> Fixes gcc '-Wunused-but-set-variable' warning:
>
> drivers/crypto/chelsio/chcr_ipsec.c: In function 'chcr_ipsec_xmit':
> drivers/crypto/chelsio/chcr_ipsec.c:674:33: warning:
> variable 'kctx_len' set but not used [-Wunused-but-set-vari
This patch adds support for crypto4xx's ANSI X9.17 Annex C compliant
pseudo random number generator which provides a pseudo random source
for the purpose of generating Initialization Vectors (IV's) for AES
algorithms to the Packet Engine and other pseudo random number
requirements.
Signed-off-by:
This series adds HiSilicon QM and ZIP controller driver in crypto subsystem.
A simple QM/ZIP driver which helps to provide an example for a general
accelerator framework is under review in community[1]. Based on this simple
driver, this series adds HW v2 support, PCI passthrough, reset, PCI/misc e
Add Zhou Wang as a maintainer for HiSilicon QM and ZIP controller driver.
Signed-off-by: Zhou Wang
Reviewed-by: John Garry
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 0767f1d..5be84e2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -
Add debugfs descriptions for HiSilicon ZIP and QM driver.
Signed-off-by: Zhou Wang
Reviewed-by: Jonathan Cameron
---
Documentation/ABI/testing/debugfs-hisi-zip | 50 ++
1 file changed, 50 insertions(+)
create mode 100644 Documentation/ABI/testing/debugfs-hisi-zip
d
The HiSilicon ZIP accelerator implements the zlib and gzip algorithm. It
uses Hisilicon QM as the interface to the CPU.
This patch provides PCIe driver to the accelerator and register it to
the crypto subsystem.
Signed-off-by: Zhou Wang
Signed-off-by: Shiju Jose
Signed-off-by: Kenneth Lee
Sign
QM is a general IP used by HiSilicon accelerators. It provides a general
PCIe interface for the CPU and the accelerator to share a group of queues.
A QM integrated in an accelerator provides queue management service. Queues
can be assigned to PF and VFs, and queues can be controlled by unified
mai
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