On 10/17/18 8:23 PM, Kees Cook wrote:
>>
>> If so, could you take this patch?
>
> Since this has no functional exposure (the sizes are the same), let's
> just wait until after the merge window to get this into crypto-next.
>
Okay. I agree.
Thanks!
--
Gustavo
On Wed, Oct 17, 2018 at 4:35 PM Horia Geanta wrote:
>
> On 9/21/2018 3:06 PM, Neil Armstrong wrote:
> > Hi,
> >
> > I recently configured dm-crypt + dm-integrity on an iMX6q platform with
> > CAAM Hash functions enabled using the following command lines :
> >
> > Linux 4.14.71
> >
> > cryptsetup
From: Eric Biggers
Make the ARM scalar AES implementation closer to constant-time by
disabling interrupts and prefetching the tables into L1 cache. This is
feasible because due to ARM's "free" rotations, the main tables are only
1024 bytes instead of the usual 4096 used by most AES implementatio
From: Eric Biggers
In the "aes-fixed-time" AES implementation, disable interrupts while
accessing the S-box, in order to make cache-timing attacks more
difficult. Previously it was possible for the CPU to be interrupted
while the S-box was loaded into L1 cache, potentially evicting the
cacheline
This series makes the "aes-fixed-time" and "aes-arm" implementations of
AES more resistant to cache-timing attacks.
Note that even after these changes, the implementations still aren't
necessarily guaranteed to be constant-time; see
https://cr.yp.to/antiforgery/cachetiming-20050414.pdf for a discu
Hi Eric,
On 17 October 2018 at 14:18, Eric Biggers wrote:
> From: Eric Biggers
>
> In the "aes-fixed-time" AES implementation, disable interrupts while
> accessing the S-box, in order to make cache-timing attacks more
> difficult. Previously it was possible for the CPU to be interrupted
> while
Hi Eric,
Thanks for looking into this.
On 17 October 2018 at 14:18, Eric Biggers wrote:
> From: Eric Biggers
>
> Make the ARM scalar AES implementation closer to constant-time by
> disabling interrupts and prefetching the tables into L1 cache. This is
> feasible because due to ARM's "free" rot
On Wed, Oct 17, 2018 at 7:41 AM, Gustavo A. R. Silva
wrote:
>
>
> On 10/17/18 9:20 AM, Antoine Tenart wrote:
>> Hi,
>>
>> On Wed, Oct 17, 2018 at 02:17:41PM +0800, Herbert Xu wrote:
>>> On Tue, Oct 16, 2018 at 09:44:02PM +0200, Gustavo A. R. Silva wrote:
On 10/9/18 12:20 AM, Kees Cook wrote:
On 10/17/18 8:17 AM, AnilKumar Chimata wrote:
> This patch adds support for Inline Crypto Engine (ICE), which
> is embedded into storage device/controller such as UFS/eMMC.
> ICE is intended for high throughput cryptographic encryption
> or decryption of storage data.
>
> Signed-off-by: AnilKumar
First, thanks for the effort for working on getting the core ICE
driver support into upstreamable patches.
On Wed, Oct 17, 2018 at 08:47:56PM +0530, AnilKumar Chimata wrote:
> +2) Per File Encryption (PFE)
> +Per File Manager(PFM) calls QSEECom api to create the key. PFM has a peer
> comp-
> +one
This patch adds support for Inline Crypto Engine (ICE), which
is embedded into storage device/controller such as UFS/eMMC.
ICE is intended for high throughput cryptographic encryption
or decryption of storage data.
Signed-off-by: AnilKumar Chimata
---
Documentation/crypto/msm/ice.txt | 235
Add dt parameters information specific to the Inline
Crypto Engine (ICE) device.
Signed-off-by: AnilKumar Chimata
---
.../devicetree/bindings/crypto/msm/ice.txt | 34 ++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/msm/
Add new syscall for ICE key config restore during
device reset, which needs to update the existing
qcom_scm_call() signature.
Signed-off-by: AnilKumar Chimata
---
drivers/firmware/qcom_scm-32.c | 30 +---
drivers/firmware/qcom_scm-64.c | 77 ++
This patch series adds support for QualComm ICE driver which
is embedded in storage device such as UFS/eMMC.
ICE HW provides high throughputs, which meets the line speed
of storage devices. ICE works in bypass or non-bypass mode,
during bypass mode ICE does not perform any crypto operations
but in
On 10/17/18 9:20 AM, Antoine Tenart wrote:
> Hi,
>
> On Wed, Oct 17, 2018 at 02:17:41PM +0800, Herbert Xu wrote:
>> On Tue, Oct 16, 2018 at 09:44:02PM +0200, Gustavo A. R. Silva wrote:
>>> On 10/9/18 12:20 AM, Kees Cook wrote:
On Mon, Oct 8, 2018 at 12:17 PM, Gustavo A. R. Silva
wrot
tree:
https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git master
head: a1c6fd4308d37f072e939a2782f24214115fc7e8
commit: 944585a64f5e37d11ff274a905304b565a88e147 [97/126] crypto: x86/aes-ni -
remove special handling of AES in PCBC mode
config: x86_64-randconfig-s4-1017181
On 9/21/2018 3:06 PM, Neil Armstrong wrote:
> Hi,
>
> I recently configured dm-crypt + dm-integrity on an iMX6q platform with CAAM
> Hash functions enabled using the following command lines :
>
> Linux 4.14.71
>
> cryptsetup luksFormat /dev/mmcblk1p3 --cipher aes-xts-plain64 --type luks2
> --i
On Wed, Oct 17, 2018 at 9:59 AM Leonard Crestez wrote:
> There is a changelog in the cover letter.
It did not show up:
https://lkml.org/lkml/2018/10/17/673
> This only looks slightly odd in git diff but it's not unrelated.
>
> I placed clk get/prepare/enable just before stmp_reset_block and mad
On Wed, 2018-10-17 at 09:48 -0300, Fabio Estevam wrote:
> On Wed, Oct 17, 2018 at 9:38 AM Leonard Crestez
> wrote:
> >
> > On 6ull and 6sll the DCP block has a clock which needs to be explicitly
> > enabled.
> >
> > Add minimal handling for this at probe/remove time.
> >
> > Signed-off-by: Leo
Hi Leonard,
On Wed, Oct 17, 2018 at 9:38 AM Leonard Crestez wrote:
>
> On 6ull and 6sll the DCP block has a clock which needs to be explicitly
> enabled.
>
> Add minimal handling for this at probe/remove time.
>
> Signed-off-by: Leonard Crestez
> ---
Please always explain what changed from the
On 6ull and 6sll the DCP block has a clock which needs to be explicitly
enabled.
Add minimal handling for this at probe/remove time.
Signed-off-by: Leonard Crestez
---
drivers/crypto/mxs-dcp.c | 28 +---
1 file changed, 25 insertions(+), 3 deletions(-)
diff --git a/driv
The DCP block on 6ull has no major differences other than requiring
explicit clock enabling.
Signed-off-by: Leonard Crestez
Reviewed-by: Fabio Estevam
---
arch/arm/boot/dts/imx6ull.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boo
This block is present in 6sl, 6sll and 6ull so it should be enabled in
the default imx kernel config.
Signed-off-by: Leonard Crestez
Reviewed-by: Fabio Estevam
---
arch/arm/configs/imx_v6_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/imx_v6_v7_defconfig
b/ar
Explicit clock enabling is required on 6sll and 6ull so mention that
standard clock bindings are used.
Signed-off-by: Leonard Crestez
Reviewed-by: Fabio Estevam
---
Documentation/devicetree/bindings/crypto/fsl-dcp.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetre
The DCP block is present on 6sll and 6ull but not enabled. The hardware is
mostly compatible with 6sl, the only important difference is that explicit
clock enabling is required.
There were several issues with the functionality of this driver (it didn't
even probe properly) but they are fixed in cr
tree:
https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git master
head: a1c6fd4308d37f072e939a2782f24214115fc7e8
commit: 944585a64f5e37d11ff274a905304b565a88e147 [97/126] crypto: x86/aes-ni -
remove special handling of AES in PCBC mode
config: x86_64-randconfig-u0-1017182
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Hi,
On Wed, Oct 17, 2018 at 02:17:41PM +0800, Herbert Xu wrote:
> On Tue, Oct 16, 2018 at 09:44:02PM +0200, Gustavo A. R. Silva wrote:
> > On 10/9/18 12:20 AM, Kees Cook wrote:
> > > On Mon, Oct 8, 2018 at 12:17 PM, Gustavo A. R. Silva
> > > wrote:
> > >> The original intention is to allocate spa
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