On Mon, Oct 08, 2018 at 02:09:37PM +0300, Horia Geantă wrote:
> CGRs (Congestion Groups) have to be freed by the same CPU that
> initialized them.
> This is why currently the driver takes special measures; however, using
> set_cpus_allowed_ptr() is incorrect - as reported by Sebastian.
>
> Instead
On Sat, Oct 13, 2018 at 01:46:56PM +0530, Harsh Jain wrote:
> Update cxgb4 to send No. of Tx Queue created in lldinfo struct
> and use the same ntxq in chcr driver.
>
> This patch depends on following commit
> commit add92a817e60e308a419693413a38d9d1e663aff
> "Fix memory corruption in DMA Mapped
On Wed, Oct 10, 2018 at 02:26:48PM +0300, Horia Geantă wrote:
> Previously, a tree-wide change added SPDX license identifiers to
> files lacking licensing information:
> b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to files
> with no license")
>
> To be consistent update th
On Wed, Oct 10, 2018 at 02:40:07PM -0700, Nathan Chancellor wrote:
> Clang warns when one enumerated type is implicitly converted to another
> and this happens in several locations in this driver, ultimately related
> to the set_cipher_{mode,config0} functions. set_cipher_mode expects a mode
> of t
On Tue, Oct 16, 2018 at 09:44:02PM +0200, Gustavo A. R. Silva wrote:
> Hi all,
>
> On 10/9/18 12:20 AM, Kees Cook wrote:
> > On Mon, Oct 8, 2018 at 12:17 PM, Gustavo A. R. Silva
> > wrote:
> >> The original intention is to allocate space for EIP197_DEFAULT_RING_SIZE
> >> *pointers* to struct, so
From: Eric Biggers
Make the ARM scalar AES implementation closer to constant-time by
disabling interrupts and prefetching the tables into L1 cache. This is
feasible because due to ARM's "free" rotations, the main tables are only
1024 bytes instead of the usual 4096 used by most AES implementatio
This series makes the "aes-fixed-time" and "aes-arm" implementations of
AES more resistant to cache-timing attacks.
Note that even after these changes, the implementations still aren't
necessarily guaranteed to be constant-time; see
https://cr.yp.to/antiforgery/cachetiming-20050414.pdf for a discu
From: Eric Biggers
In the "aes-fixed-time" AES implementation, disable interrupts while
accessing the S-box, in order to make cache-timing attacks more
difficult. Previously it was possible for the CPU to be interrupted
while the S-box was loaded into L1 cache, potentially evicting the
cacheline
On Fri, Oct 12, 2018 at 09:41:05AM +0300, Vitaly Chikunov wrote:
>
> It is the first part of attempts to add to the Integrity subsystem
> ability of verifying file and module signatures by Russian GOST
> algorithms.
It would be better if these patches are posted together. That
way we don't end up
Hi Ard,
On Thu, Oct 04, 2018 at 08:55:14AM +0200, Ard Biesheuvel wrote:
> Hi Eric,
>
> On 4 October 2018 at 06:07, Eric Biggers wrote:
> > From: Eric Biggers
> >
> > The generic constant-time AES implementation is supposed to preload the
> > AES S-box into the CPU's L1 data cache. But, an inte
On Wed, Oct 10, 2018 at 03:12:51PM +0300, Vitaly Chikunov wrote:
> Add GOST/IETF Streebog hash function (GOST R 34.11-2012, RFC 6986)
> generic hash transformation.
>
> Signed-off-by: Vitaly Chikunov
> ---
> crypto/Kconfig| 12 +
> crypto/Makefile |1 +
> crypto/stree
On Wed, Oct 10, 2018 at 03:12:52PM +0300, Vitaly Chikunov wrote:
> Add testmgr and tcrypt tests and vectors for Streebog hash function
> from RFC 6986 and GOST R 34.11-2012.
>
> Signed-off-by: Vitaly Chikunov
> ---
> crypto/tcrypt.c | 27 +
> crypto/testmgr.c | 12 ++
Hi all,
On 10/9/18 12:20 AM, Kees Cook wrote:
> On Mon, Oct 8, 2018 at 12:17 PM, Gustavo A. R. Silva
> wrote:
>> The original intention is to allocate space for EIP197_DEFAULT_RING_SIZE
>> *pointers* to struct, so sizeof(priv->ring[i].rdr_req) should be
>> sizeof(*priv->ring[i].rdr_req).
>>
>> Ad
On Tue, 2018-10-16 at 13:03 -0300, Fabio Estevam wrote:
> > + /* DCP clock is optional, only used on some SOCs */
> > + sdcp->dcp_clk = devm_clk_get(dev, "dcp");
> > + if (IS_ERR(sdcp->dcp_clk)) {
> > + if (sdcp->dcp_clk != ERR_PTR(-ENOENT))
> > +
On Tue, Oct 16, 2018 at 12:59 PM Leonard Crestez
wrote:
>
> The DCP block on 6ull has no major differences other than requiring
> explicit clock enabling.
>
> Signed-off-by: Leonard Crestez
Reviewed-by: Fabio Estevam
Hi Leonard,
On Tue, Oct 16, 2018 at 12:58 PM Leonard Crestez
wrote:
> + /* DCP clock is optional, only used on some SOCs */
> + sdcp->dcp_clk = devm_clk_get(dev, "dcp");
> + if (IS_ERR(sdcp->dcp_clk)) {
> + if (sdcp->dcp_clk != ERR_PTR(-ENOENT))
> +
This block is present in 6sl, 6sll and 6ull so it should be enabled in
the default imx kernel config.
Signed-off-by: Leonard Crestez
Reviewed-by: Fabio Estevam
---
arch/arm/configs/imx_v6_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/imx_v6_v7_defconfig
b/ar
On 6ull and 6sll the DCP block has a clock which needs to be explicitly
enabled.
Add minimal handling for this at probe/remove time.
Signed-off-by: Leonard Crestez
---
drivers/crypto/mxs-dcp.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/crypto/mxs-dcp.c b/driver
The DCP block on 6ull has no major differences other than requiring
explicit clock enabling.
Signed-off-by: Leonard Crestez
---
arch/arm/boot/dts/imx6ull.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi
index 796
Explicit clock enabling is required on 6sll and 6ull so mention that
standard clock bindings are used.
Signed-off-by: Leonard Crestez
Reviewed-by: Fabio Estevam
---
Documentation/devicetree/bindings/crypto/fsl-dcp.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetre
The DCP block is present on 6sll and 6ull but not enabled. The hardware is
mostly compatible with 6sl, the only important difference is that explicit
clock enabling is required.
There were several issues with the functionality of this driver (it didn't
even probe properly) but they are fixed in cr
Add support for SM4 cipher in CryptoCell 713.
Signed-off-by: Gilad Ben-Yossef
---
drivers/crypto/Kconfig | 1 +
drivers/crypto/ccree/cc_cipher.c| 66 +
drivers/crypto/ccree/cc_hw_queue_defs.h | 3 ++
3 files changed, 70 insertions(+)
di
Add device tree bindings associating Arm TrustZone CryptoCell 713 with the
ccree driver.
Signed-off-by: Gilad Ben-Yossef
---
Documentation/devicetree/bindings/crypto/arm-cryptocell.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/cryp
Add support for Arm TrustZone CryptoCell 713.
Note that this patch just enables using a 713 in backwards compatible mode
to 712. Newer 713 specific features will follow.
Signed-off-by: Gilad Ben-Yossef
---
drivers/crypto/Kconfig | 2 +-
drivers/crypto/ccree/cc_driver.c | 23 ++
Add first batch of patches for support of Arm TrustZone CryptoCell 713.
Gilad Ben-Yossef (3):
crypto: ccree: add support for CryptoCell 713
crypto: ccree: add dt bindings for ccree 713
crypto: ccree: add SM4 support
.../devicetree/bindings/crypto/arm-cryptocell.txt | 5 +-
drivers/crypto
From: Andy Lutomirski
commit c592b57347069abfc0dcad3b3a302cf882602597 upstream.
This removes all the obvious code paths that depend on lazy FPU mode.
It shouldn't change the generated code at all.
Signed-off-by: Andy Lutomirski
Signed-off-by: Rik van Riel
Cc: Borislav Petkov
Cc: Brian Gerst
26 matches
Mail list logo
