Hi Stefan,
The change looks to be fine. From the IP point of view its using the
same values in case of AES cipher and hash types so explicit casting
should be ok.
-Raveendra
On Sat, Mar 24, 2018 at 4:32 PM, Stefan Agner wrote:
> In the AES cases enum spu_cipher_type and enum hash_type have
> t
On 3/27/2018 11:53 PM, Stefano Brivio wrote:
> On Tue, 27 Mar 2018 23:06:30 +0530
> Atul Gupta wrote:
>
>> +static struct tls_context *create_ctx(struct sock *sk)
>> +{
>> +struct inet_connection_sock *icsk = inet_csk(sk);
>> +struct tls_context *ctx;
>> +
>> +/* allocate tls context
On 3/27/2018 11:12 PM, Stefano Brivio wrote:
> On Tue, 27 Mar 2018 23:06:37 +0530
> Atul Gupta wrote:
>
>> Exchange messages with hardware to program the TLS session
>> CPL handlers for messages received from chip.
>>
>> Signed-off-by: Atul Gupta
>> Signed-off-by: Michael Werner
>> Reviewed-by
On 3/28/2018 2:14 AM, Sabrina Dubroca wrote:
> 2018-03-27, 23:06:31 +0530, Atul Gupta wrote:
>> Ethtool option enables TLS record offload on HW, user
>> configures the feature for netdev capable of Inline TLS.
>> This allows user to define custom sk_prot for Inline TLS sock
>>
>> Signed-off-by: A
Add support for io{read|write}64() functions in parisc architecture.
These are pretty straightforward copies of similar functions which
make use of readq and writeq.
Also, indicate that the lo_hi and hi_lo variants of these functions
are not provided by this architecture.
Signed-off-by: Logan Gun
Clean up the ifdefs which conditionally defined the io{read|write}64
functions in favour of the new common io-64-nonatomic-lo-hi header.
Per a nit from Andy Shevchenko, the include list is also made
alphabetical.
Signed-off-by: Logan Gunthorpe
Reviewed-by: Andy Shevchenko
Cc: Jon Mason
---
dr
This is v14 of my cleanup series to push a number of instances of people
defining their own io{read|write}64 functions into common headers seing
they don't exist in non-64bit systems. This series adds inline functions to the
io-64-nonatomic headers and then cleans up the drivers that defined their
Now that ioread64 and iowrite64 are available in io-64-nonatomic,
we can remove the hack at the top of ntb_hw_intel.c and replace it
with an include.
Signed-off-by: Logan Gunthorpe
Reviewed-by: Andy Shevchenko
Acked-by: Dave Jiang
Acked-by: Allen Hubbe
Acked-by: Jon Mason
---
drivers/ntb/hw/
Fix an asymmetry in the io{read|write}XXbe functions in that the
big-endian variants make use of the raw io accessors while the
little-endian variants use the regular accessors. Some architectures
implement barriers to order against both spinlocks and DMA accesses
and for these case, the big-endian
This patch adds generic io{read|write}64[be]{_lo_hi|_hi_lo} macros if
they are not already defined by the architecture. (As they are provided
by the generic iomap library).
The patch also points io{read|write}64[be] to the variant specified by the
header name.
This is because new drivers are enco
Clean up the extra ifdefs which defined the wr_reg64 and rd_reg64
functions in non-64bit cases in favour of the new common
io-64-nonatomic-lo-hi header.
To be consistent with CAAM engine HW spec: in case of 64-bit registers,
irrespective of device endianness, the lower address should be read from
Subsequent patches in this series makes use of the readq and writeq
defines in iomap.h. However, as is, they get missed on the powerpc
platform seeing the include comes before the define. This patch
moves the include down to fix this.
Signed-off-by: Logan Gunthorpe
Acked-by: Michael Ellerman
Rev
In order to provide non-atomic functions for io{read|write}64 that will
use readq and writeq when appropriate. We define a number of variants
of these functions in the generic iomap that will do non-atomic
operations on pio but atomic operations on mmio.
These functions are only defined if readq a
These functions will be introduced into the generic iomap.c so
they can deal with PIO accesses in hi-lo/lo-hi variants. Thus,
the powerpc version of iomap.c will need to provide the same
functions even though, in this arch, they are identical to the
regular io{read|write}64 functions.
Signed-off-b
My name is Charles Koch Foundation, A philanthropist the CEO and Chairman of
the Charles Koch Foundation Charitable Foundation, one of the largest private
foundations in the world. I believe strongly in‘giving while living' I had one
idea that never changed in my mind - that you should use your
2018-03-27, 23:06:31 +0530, Atul Gupta wrote:
> Ethtool option enables TLS record offload on HW, user
> configures the feature for netdev capable of Inline TLS.
> This allows user to define custom sk_prot for Inline TLS sock
>
> Signed-off-by: Atul Gupta
> Reviewed-by: Sabrina Dubroca
uh, what?
--
Greeting, once again is me Lucy Boston this is twice am contacting you
please is very urgent respond to me for more details through my.
Email:
dr.lucybos...@gmail.com
On Tue, 27 Mar 2018 23:06:30 +0530
Atul Gupta wrote:
> +static struct tls_context *create_ctx(struct sock *sk)
> +{
> + struct inet_connection_sock *icsk = inet_csk(sk);
> + struct tls_context *ctx;
> +
> + /* allocate tls context */
> + ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
>
On Tue, 27 Mar 2018 23:06:36 +0530
Atul Gupta wrote:
> +static void __set_tcb_field(struct sock *sk, struct sk_buff *skb, u16 word,
> + u64 mask, u64 val, u8 cookie, int no_reply)
> +{
> + struct chtls_sock *csk = rcu_dereference_sk_user_data(sk);
> + struct cpl_se
On Tue, 27 Mar 2018 23:06:38 +0530
Atul Gupta wrote:
> +static u8 tcp_state_to_flowc_state(u8 state)
> +{
> + u8 ret = FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED;
> +
> + switch (state) {
> + case TCP_ESTABLISHED:
> + ret = FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED;
> + break
On Tue, 27 Mar 2018 23:06:37 +0530
Atul Gupta wrote:
> Exchange messages with hardware to program the TLS session
> CPL handlers for messages received from chip.
>
> Signed-off-by: Atul Gupta
> Signed-off-by: Michael Werner
> Reviewed-by: Sabrina Dubroca
> Reviewed-by: Stefano Brivio
No, I
On Tue, 27 Mar 2018 23:06:38 +0530
Atul Gupta wrote:
> TLS handler for record transmit.
> Create Inline TLS work request and post to FW.
> Create Inline TLS record CPLs for hardware
>
> Signed-off-by: Atul Gupta
> Signed-off-by: Michael Werner
> Reviewed-by: Stefano Brivio
Absolutely not.
-
On Tue, 27 Mar 2018 23:06:36 +0530
Atul Gupta wrote:
> Initialize the space reserved for storing the TLS keys,
> get and free the location where key is stored for the TLS
> connection.
> Program the Tx and Rx key as received from user in
> struct tls12_crypto_info_aes_gcm_128 and understood by ha
handler for record receive. plain text copied to user
buffer
Signed-off-by: Atul Gupta
Signed-off-by: Michael Werner
---
drivers/crypto/chelsio/chtls/chtls_io.c | 592
1 file changed, 592 insertions(+)
diff --git a/drivers/crypto/chelsio/chtls/chtls_io.c
b/dri
Entry for Inline TLS as another driver dependent on cxgb4 and chcr
Signed-off-by: Atul Gupta
---
drivers/crypto/chelsio/Kconfig| 11 +++
drivers/crypto/chelsio/Makefile | 1 +
drivers/crypto/chelsio/chtls/Makefile | 4
3 files changed, 16 insertions(+)
create mode 1
Register chtls as Inline TLS driver, chtls is ULD to cxgb4.
Setsockopt to program (tx/rx) keys on chip.
Support AES GCM of key size 128.
Support both Inline Rx and Tx.
Signed-off-by: Atul Gupta
Reviewed-by: Casey Leedom
Reviewed-by: Michael Werner
---
drivers/crypto/chelsio/chtls/chtls_main.c
TLS handler for record transmit.
Create Inline TLS work request and post to FW.
Create Inline TLS record CPLs for hardware
Signed-off-by: Atul Gupta
Signed-off-by: Michael Werner
Reviewed-by: Stefano Brivio
---
drivers/crypto/chelsio/chtls/chtls_io.c | 1228 +++
1 f
Initialize the space reserved for storing the TLS keys,
get and free the location where key is stored for the TLS
connection.
Program the Tx and Rx key as received from user in
struct tls12_crypto_info_aes_gcm_128 and understood by hardware.
added socket option TLS_RX
Signed-off-by: Atul Gupta
Re
Exchange messages with hardware to program the TLS session
CPL handlers for messages received from chip.
Signed-off-by: Atul Gupta
Signed-off-by: Michael Werner
Reviewed-by: Sabrina Dubroca
Reviewed-by: Stefano Brivio
---
drivers/crypto/chelsio/chtls/chtls_cm.c | 2057
Read the Inline TLS capability from firmware.
Determine the area reserved for storing the keys
Dump the Inline TLS tx and rx records count.
Signed-off-by: Atul Gupta
Reviewed-by: Michael Werner
Reviewed-by: Casey Leedom
---
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c | 32 ++--
driver
Define macro for programming the TLS Key context
Signed-off-by: Atul Gupta
---
drivers/crypto/chelsio/chcr_algo.h | 42 +
drivers/crypto/chelsio/chcr_core.h | 55 +-
2 files changed, 96 insertions(+), 1 deletion(-)
diff --git a/dri
Ethtool option enables TLS record offload on HW, user
configures the feature for netdev capable of Inline TLS.
This allows user to define custom sk_prot for Inline TLS sock
Signed-off-by: Atul Gupta
Reviewed-by: Sabrina Dubroca
---
include/linux/netdev_features.h | 2 ++
net/core/ethtool.c
Define Inline TLS state, connection management info.
Supporting macros definition.
Signed-off-by: Atul Gupta
Reviewed-by: Sabrina Dubroca
Reviewed-by: Michael Werner
---
drivers/crypto/chelsio/chtls/chtls.h| 483
drivers/crypto/chelsio/chtls/chtls_cm.h | 20
Key area size in hw-config file. CPL struct for TLS request
and response. Work request for Inline TLS.
Signed-off-by: Atul Gupta
Reviewed-by: Casey Leedom
---
drivers/net/ethernet/chelsio/cxgb4/t4_msg.h | 122 ++-
drivers/net/ethernet/chelsio/cxgb4/t4_regs.h | 2 +
drivers/
Facility to register Inline TLS drivers to net/tls. Setup
TLS_HW_RECORD prot to listen on offload device.
Cases handled
- Inline TLS device exists, setup prot for TLS_HW_RECORD
- Atleast one Inline TLS exists, sets TLS_HW_RECORD.
- If non-inline device establish connection, move to TLS_SW_TX
Sign
"Thank you, Stefano, Sabrina, Dave W. and everyone for reviewing the series."
"Dave, this should apply clean on net-next tree and I think it is ready
to merge".
Series for Chelsio Inline TLS driver (chtls)
Use tls ULP infrastructure to register chtls as Inline TLS driver.
Chtls use TCP Sockets t
Hi Tero,
> Also, I think this patch should be split up in two, as there are two
> issues you are fixing; the bad pointer issue (which I think you only
> fixed partially, also the in->sgl has similar problem), and the missing
> output IVI. Why is this needed btw, I have never faced the requirement
Hi Tero,
> I have a couple of additional comments, but can't add them as the patch
> content is an attachment (like, I would not add the WARN_ON.) Overall,
> the issue you have found is a legitimate problem, and should be fixed.
I have used WARN_ON() to have some very visible output, I agree it i
On Fri, Mar 23, 2018 at 02:09:46PM -0500, Gustavo A. R. Silva wrote:
>
> Hi Herbert,
>
> There is an ongoing effort to remove all VLAs from the code base [1] and
> while working on that I came across the following macro at
> include/crypto/hash.h:154:
>
> #define SHASH_DESC_ON_STACK(shash, ctx)
Hi Milan,
I will run veritysetup test on next version of these patches and contact you
about verity-compat-test testsuits.
Thank you,
Yael
-Original Message-
From: Milan Broz
Sent: Tuesday, 27 March 2018 11:05
To: Eric Biggers ; Yael Chemla ;
Mike Snitzer
Cc: Alasdair Kergon ; dm-de..
Hi Eric,
Thanks for the detailed feedback, I'll have a look at how dm-crypt avoid
dynamic allocation per-bio, and also do forward error correction tests.
Yael
-Original Message-
From: Eric Biggers
Sent: Tuesday, 27 March 2018 9:55
To: Yael Chemla
Cc: Alasdair Kergon ; Mike Snitzer ;
Mike and others,
did anyone even try to run veritysetup tests?
We have verity-compat-test in our testsuite, is has even basic FEC tests
included.
We just added userspace verification of FEC RS codes to compare if kernel
behaves the same.
I tried to apply three last dm-verity patches from your
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