From: Herbert Xu
Date: Thu, 5 Oct 2017 11:40:54 +0800
> On Tue, Oct 03, 2017 at 07:45:06PM -0300, Marcelo Ricardo Leitner wrote:
>>
>> > Usually if you're invoking setkey from a non-sleeping code-path
>> > you're probably doing something wrong.
>>
>> Usually but not always. There are 3 calls to
On Tue, Oct 03, 2017 at 07:45:06PM -0300, Marcelo Ricardo Leitner wrote:
>
> > Usually if you're invoking setkey from a non-sleeping code-path
> > you're probably doing something wrong.
>
> Usually but not always. There are 3 calls to that function on SCTP
> code:
> - pack a cookie, which is sent
On Tue, Oct 03, 2017 at 07:48:08AM +, Fabien DESSENNE wrote:
>
> It looks like there is no more activity around this "crypto_engine
> interface clean up" task.
> This unfortunately has been blocking the introduction of this new STM32
> crypto driver for 3 months now.
> Would it make sense to
On 10/04/2017 04:47 PM, Borislav Petkov wrote:>
Signed-off-by: Borislav Petkov
Signed-off-by: Brijesh Singh
i.e., the first SOB is the author's and the second is yours which means,
you've handled the patch further on, like sending it upstream, for
example.
Noted, thanks
On Wed, Oct 04, 2017 at 08:13:50AM -0500, Brijesh Singh wrote:
> From: Borislav Petkov
>
> This is AMD-specific hardware so present it in Kconfig only when AMD
> CPU support is enabled or on ARM64 where it is also used.
>
> Signed-off-by:
> Signed-off-by: Borislav Petkov
For the future, when
From: Suniel Mahesh
There is no need to create a local pointer variable "dev" and
pass it various API's, instead use plat_dev which is enumerated
by platform core on successful probe.
Signed-off-by: Suniel Mahesh
---
Note:
- Patch was tested and built(ARCH=arm) on staging-testing.
- No build is
Add support for MD5, SHA1, SHA256 hash algorithms for Exynos HW.
It uses the crypto framework asynchronous hash api.
It is based on omap-sham.c driver.
S5P has some HW differencies and is not implemented.
Modifications in s5p-sss:
- Add hash supporting structures and functions.
- Modify irq hand
On 03.10.2017 21:30, Krzysztof Kozlowski wrote:
> On Tue, Oct 03, 2017 at 04:57:43PM +0200, Kamil Konieczny wrote:
>
[...]
+static struct ahash_alg algs_sha256[] = {
+{
+ .init = s5p_hash_init,
+ .update = s5p_hash_update,
+ .final = s5p
On Wed, Oct 04, 2017 at 12:48:53PM +0200, Marcin Nowakowski wrote:
> arch/mips/Kconfig | 4 +
> arch/mips/Makefile| 3 +
> arch/mips/crypto/Makefile | 5 +
> arch/mips/crypto/crc32-mips.c | 364
> ++
> crypto/Kconfig
On Wed, Oct 04, 2017 at 11:21:53AM +0200, Borislav Petkov wrote:
> On Wed, Oct 04, 2017 at 12:26:11PM +0530, P J P wrote:
> > Each return above needs to be on its own line.
>
> ... because?
It's actually readable by humanѕ that way.
From: Borislav Petkov
This is AMD-specific hardware so present it in Kconfig only when AMD
CPU support is enabled or on ARM64 where it is also used.
Signed-off-by:
Signed-off-by: Borislav Petkov
Cc: Brijesh Singh
Cc: Tom Lendacky
Cc: Gary Hook
Cc: Herbert Xu
Cc: "David S. Miller"
Cc: linu
The Platform Security Processor (PSP) is part of AMD Secure Processor
(AMD-SP), PSP is a dedicated processor that provides the support for
key management commands in a Secure Encrypted Virtualization (SEV) mode,
along with software-based Trusted Execution Environment (TEE) to enable
the third-party
AMDs new Secure Encrypted Virtualization (SEV) feature allows the memory
contents of a virtual machines to be transparently encrypted with a key
unique to the guest VM. The programming and management of the encryption
keys are handled by the AMD Secure Processor (AMD-SP), which exposes the
commands
Define Secure Encrypted Virtualization (SEV) key management command id
and structure. The command definition is available in SEV KM [1] spec
0.14.
[1] http://support.amd.com/TechDocs/55766_SEV-KM API_Specification.pdf
Cc: Paolo Bonzini
Cc: "Radim Krčmář"
Cc: Borislav Petkov
Cc: Herbert Xu
Cc:
This part of Secure Encryted Virtualization (SEV) patch series focuses on KVM
changes required to create and manage SEV guests.
SEV is an extension to the AMD-V architecture which supports running encrypted
virtual machine (VMs) under the control of a hypervisor. Encrypted VMs have
their
pages (c
I am getting in touch with you regarding an extremely important and urgent
matter. If you would oblige me the opportunity, I shall provide you with
details upon your
response.
Fix the wrong index number when checking the existence of second
id in function of finding asymmetric key. The id_1 is the second
id that the index in array must be 1 but not 0.
Fix: 9eb029893(KEYS: Generalise x509_request_asymmetric_key())
Cc: David Howells
Cc: Herbert Xu
Cc: "David S. Miller"
On 03/10/17 23:16, David Woodhouse wrote:
> On Tue, 2017-10-03 at 19:05 +0100, Robin Murphy wrote:
>>
>> Now, there are indeed plenty of drivers and subsystems which do work on
>> lists of explicitly single pages - anything doing some variant of
>> "addr = kmap_atomic(sg_page(sg)) + sg->offset;" is
On Wed, Oct 04, 2017 at 04:12:37PM +0530, P J P wrote:
> Quick glance would work if it is readable. Currently it is not if
> one is viewing it in 80 cols screen/window. They do that. Writing
> return on the same line does not add specific value IMO.
Then you'll have to scroll to the right like y
This module registers crc32 and crc32c algorithms that use the
optional CRC32[bhwd] and CRC32C[bhwd] instructions in MIPSr6 cores.
Signed-off-by: Marcin Nowakowski
Cc: linux-crypto@vger.kernel.org
Cc: Herbert Xu
Cc: "David S. Miller"
---
v2:
- minor code refactoring as suggested by JamesH whi
+-- On Wed, 4 Oct 2017, Borislav Petkov wrote --+
| This is a function which maps commands to buffer lengths and it should be
| obvious at a *very* quick glance what it does. And that is best done if it
| is written in a tabular manner as we do such things in other places in the
| kernel too.
On Wed, Oct 04, 2017 at 03:24:36PM +0530, P J P wrote:
> It appears to cross 80 columns limit, checkpatch.pl throws warnings. Adding
> new line would be consistent with coding style.
The 80 cols rule is not a hard one and checkpatch should not override
common sense. This is a function which maps
+-- On Wed, 4 Oct 2017, Borislav Petkov wrote --+
| On Wed, Oct 04, 2017 at 12:26:11PM +0530, P J P wrote:
| > Each return above needs to be on its own line.
|
| ... because?
It appears to cross 80 columns limit, checkpatch.pl throws warnings. Adding
new line would be consistent with coding style
On Wed, Oct 04, 2017 at 12:26:11PM +0530, P J P wrote:
> Each return above needs to be on its own line.
... because?
--
Regards/Gruss,
Boris.
SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284
(AG Nürnberg)
--
On Wed, Oct 04, 2017 at 12:06:42PM +0530, P J P wrote:
> Needs to kfree(sp->psp_data) before setting to NULL.
Not if it is allocated with devm_kzalloc().
--
Regards/Gruss,
Boris.
SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284
(AG Nürnberg)
--
For finding asymmetric key, the input id_0 and id_1 parameters can
not be NULL at the same time. This patch adds the BUG_ON checking
for id_0 and id_1.
Cc: David Howells
Cc: Herbert Xu
Cc: "David S. Miller"
Signed-off-by: "Lee, Chun-Yi"
---
crypto/asymmetric_keys/asymmetric_type.c | 2 ++
1 f
Hi James,
On 03.10.2017 08:38, Marcin Nowakowski wrote:
The need for 64-bit signed length is unfortunate. Do you get decent
assembly and comparable/better performance on 32-bit if you just use len
and only decrement it in the loops? i.e.
- while ((length -= sizeof(uXX)) >= 0) {
+
From: Suniel Mahesh
Platform devices are expected to use wrapper functions,
platform_{get,set}_drvdata() with platform_device as argument,
for getting and setting the driver data. dev_{get,set}_drvdata()
are using &plat_dev->dev.
For wrapper functions we can directly pass a struct platform_device
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